Abstract: The present disclosure discloses a memory access interface device. A clock generation circuit generates reference signals. A transmitter transmits an output command and address signal to a memory device according to the reference signals. A signal training circuit executes a training process in a training mode that includes steps outlined below. A training signal is generated such that the training signal is transmitted as the output command and address signal. The training signal and the data signal generated by the memory device are compared to generate a comparison result indicating whether the data signal matches the training signal. The comparison result is stored. The clock generation circuit is controlled to modify a phase of at least one of the reference signals to be one of a plurality of under-test phases to execute a new loop of the training process until all the under-test phases are trained.

Abstract: The present disclosure discloses a memory access interface device. A clock generation circuit generates reference clock signals. Each of access signal transmission circuits each includes a duty cycle adjusting circuit, a duty cycle detection circuit, a frequency division circuit and an asynchronous first-in-first-out circuit. The duty cycle adjusting circuit performs duty cycle adjustment on one of the reference clock signals according to a duty cycle detection signal to generate an output clock signal having a duty cycle. The duty cycle detection circuit detects a variation of the duty cycle to generate the duty cycle detection signal. The frequency division circuit divides a frequency of the output clock signal to generate a read clock signal. The asynchronous first-in-first-out circuit receives an access signal from a memory access controller and outputs an output access signal according to the read clock signal to access the memory device accordingly.

Abstract: In some embodiments, a system for flexible non-volatile memory express drive management can include a first controller including a first drive register and a second drive register, a first processor communicatively coupled with the first drive register via a first serial bus, and a second processor communicatively coupled with the second drive register via a second serial bus. The system can also include a first set of non-volatile memory express drives communicatively coupled with the first processor via the first drive register, and a second set of non-volatile memory express drives communicatively coupled with the second processor via the second drive register and the second serial bus.

Abstract: In some embodiments, a system for flexible non-volatile memory express drive management can include a first controller including a first drive register and a second drive register, a first processor communicatively coupled with the first drive register via a first serial bus, and a second processor communicatively coupled with the second drive register via a second serial bus. The system can also include a first set of non-volatile memory express drives communicatively coupled with the first processor via the first drive register, and a second set of non-volatile memory express drives communicatively coupled with the second processor via the second drive register and the second serial bus.