Abstract: A highly compact nonvolatile solid state memory core is provided that stores and reproduces both digital and analog signals for multimedia applications. The memory core includes vertical electrically erasable and programmable read only memories (EEPROM) cells having, for example, a stacked gate or a split channel configuration. An array of EEPROM cells on the same chip is prewritten and is used as a reference for digital-analog conversions and for memory cell programming. An intelligent write method allows each memory cell to either store an analog signal or multiple digital signals. Based on the previously stored signal, the intelligent write method determines whether to charge or to discharge the floating gate associated with the selected memory cell. Thus, full erasure is not required prior to programming each memory cell. The present invention significantly increases the density of memory cell arrays while prolonging the useful life of the array.

Abstract: Disclosed is a (4T-2R) SRAM cell and method which achieves a much reduced cell area through the combined use of vertical trench pull-down n-channel transistors and a buried-layer ground plate. The reduced cell area allows the fabrication of a higher density SRAM for a given set of lithographic rules. The cell structure also allows the implementation of a (6T) SRAM cell with non-self-aligned poly-silicon p-channel pull-up transistors without appreciably enlarging the cell area.