Patents by Inventor Chun Cho

Chun Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240168298
    Abstract: Disclosed are systems and methods for superimposing a virtual image on a real-time image. A system for superimposing a virtual image on a real-time image comprises a real-time image module and a virtual image module. The real-time image module comprises a magnification assembly to generate a real-time image of an object at a first location and a first depth, with a predetermined magnification. The virtual image module generates a virtual image by respectively projecting a right light signal to a viewer's right eye and a corresponding left light signal to a viewer's left eye. The right light signal and the corresponding left light signal are perceived by the viewer to display the virtual image at a second location and a second depth. The second depth is related to an angle between the right light signal and the corresponding left light signal projected to the viewer's eyes. The second depth may be approximately the same as the first depth.
    Type: Application
    Filed: November 15, 2023
    Publication date: May 23, 2024
    Applicant: HES IP HOLDINGS, LLC
    Inventors: Feng-Chun YEH, Yin CHANG, Guo-Hsuan CHEN, Chun Hung CHO
  • Patent number: 11990100
    Abstract: An e-paper identification card system including an e-paper identification card and a data updating apparatus is provided. The e-paper identification card is configured to display first image information. The data updating apparatus is electrically connected to the e-paper identification card. The data updating apparatus is configured to update the e-paper identification card according to the first image information to drive the e-paper identification card to display second image information. In addition, an e-paper identification card is also provided.
    Type: Grant
    Filed: January 12, 2023
    Date of Patent: May 21, 2024
    Assignee: E Ink Holdings Inc.
    Inventors: Chih-Chun Chen, Huei-Chuan Lee, Cheng-Hsien Lin, Shuo-En Lee, Kai-Yi Cho
  • Publication number: 20240161481
    Abstract: A LiDAR and camera data fusion method includes generating a voxel-wise feature map based on point cloud data of a LiDAR sensor, generating a pixel-wise feature map based on image data of a camera, converting three-dimensional (3D) coordinates of point data of the voxel-wise feature map to two-dimensional (2D) coordinates, based on at least one predefined calibration parameter, and generating fused data by combining pixel data of the pixel-wise feature map and point data of the 2D coordinates.
    Type: Application
    Filed: November 16, 2023
    Publication date: May 16, 2024
    Applicants: HYUNDAI MOTOR COMPANY, Kia Corporation, Konkuk University Industrial Cooperation Corp
    Inventors: Sung Moon JANG, Ki Chun JO, Jin Su HA, Ha Min SONG, Chan Soo KIM, Ji Eun CHO
  • Patent number: 11977249
    Abstract: An optical device is provided. The optical device includes a ring waveguide and a bus waveguide. The ring waveguide includes a coupling region. The bus waveguide is disposed adjacent to and spaced apart from the coupling region of the ring waveguide. The bus waveguide includes a coupling structure corresponding to the coupling region.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Cheng-Tse Tang, Chewn-Pu Jou, Lan-Chou Cho, Ming Yang Jung, Tai-Chun Huang
  • Publication number: 20240134292
    Abstract: A substrate treatment apparatus according to an aspect of the present invention includes: a support plate that supports a substrate and is provided with a heater member for heating the substrate; and a cooling unit for forcedly cooling the support plate, wherein the cooling unit includes: a cooling housing to provide a cooling space; a plurality of gas feed nozzles that is arranged in the cooling housing and supplies cooling gas toward the heater member; and a plurality of gas feed lines that is directly connected to the gas feed nozzles and supplies the cooling gas transferred from the outside to the gas feed nozzles.
    Type: Application
    Filed: October 4, 2023
    Publication date: April 25, 2024
    Applicant: SEMES CO., LTD.
    Inventors: Minhee CHO, Hee Man AHN, Gyeong Won SONG, Jumi LEE, Chun Woo PARK, Byung Hwi KIM
  • Patent number: 11948863
    Abstract: A package structure and method of forming the same are provided. The package structure includes a polymer layer, a redistribution layer, a die, and an adhesion promoter layer. The redistribution layer is disposed over the polymer layer. The die is sandwiched between the polymer layer and the redistribution layer. The adhesion promoter layer, an oxide layer, a through via, and an encapsulant are sandwiched between the polymer layer and the redistribution layer. The encapsulant is laterally encapsulates the die. The through via extends through the encapsulant. The adhesion promoter layer and the oxide layer are laterally sandwiched between the through via and the encapsulant. A bottom portion of the encapsulant is longitudinally sandwiched between the adhesion promoter layer and the polymer layer.
    Type: Grant
    Filed: February 8, 2023
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Chun Cho, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Wei-Chih Chen
  • Publication number: 20240103606
    Abstract: The present disclosure relates to systems and methods for real and virtual object interactions in augmented reality environments are disclosed. The system comprises areal object detection module to receive multiple image pixels and the corresponding depths of at least one initiative object, a real object recognition module to determine a shape, a position, and a movement of the initiative object; a virtual object display module to display a virtual target object, a collision module to determine whether the at least one initiative object collides into a virtual target object and, an interaction module for determining an action responding to an event based on at least one of an object recognition determination from the real object recognition module, a collision determination from the collision module, and a type of the virtual target object.
    Type: Application
    Filed: January 25, 2022
    Publication date: March 28, 2024
    Applicant: HES IP HOLDINGS, LLC
    Inventors: Yung-Chin HSIAO, Ya-Chun CHOU, Shan-Ni HSIEH, Chun-Hung CHO, Te-Jen KUNG, I-Chun YEH
  • Publication number: 20240090343
    Abstract: The present disclosure relates to a magneto-resistive random access memory (MRAM) cell having an extended upper electrode, and a method of formation. In some embodiments, the MRAM cell has a magnetic tunnel junction (MTJ) arranged over a conductive lower electrode. A conductive upper electrode is arranged over the magnetic tunnel junction. Below the conductive lower electrode is a first conductive via structure in a first dielectric layer. Below the conductive via structure is a discrete conductive jumper structure in a second dielectric layer. A dielectric body of a third dielectric material that is different from the first dielectric material and the second dielectric material extends vertical from the first dielectric layer at least partially into the second dielectric layer.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Inventors: Jun-Yao CHEN, Chun-Heng LIAO, Hung Cho WANG
  • Publication number: 20230369288
    Abstract: A semiconductor package includes a semiconductor die and a redistribution structure. The semiconductor die is laterally surrounded by a molding compound, and the semiconductor die has a conductive pillar and a complex compound sheath sandwiched between the conductive pillar and the molding compound. The redistribution structure is electrically connected with the semiconductor die and comprises a first via portion at a first side of the redistribution structure and a second via portion at a second side of the redistribution structure, and a base angle of the second via portion is greater than a base angle of the first via portion.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 16, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chih Chen, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Hung-Chun Cho
  • Patent number: 11791313
    Abstract: A semiconductor package includes a semiconductor die and a redistribution structure. The semiconductor die is laterally surrounded by a molding compound, and the semiconductor die has a conductive pillar and a complex compound sheath sandwiched between the conductive pillar and the molding compound. The redistribution structure is electrically connected with the semiconductor die and comprises a first via portion at a first side of the redistribution structure and a second via portion at a second side of the redistribution structure, and a base angle of the second via portion is greater than a base angle of the first via portion.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: October 17, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chih Chen, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Hung-Chun Cho
  • Publication number: 20230317664
    Abstract: In an embodiment, a device includes: a semiconductor die including a semiconductor material; a through via adjacent the semiconductor die, the through via including a metal; an encapsulant around the through via and the semiconductor die, the encapsulant including a polymer resin; and an adhesion layer between the encapsulant and the through via, the adhesion layer including an adhesive compound having an aromatic compound and an amino group, the amino group bonded to the polymer resin of the encapsulant, the aromatic compound bonded to the metal of the through via, the aromatic compound being chemically inert to the semiconductor material of the semiconductor die.
    Type: Application
    Filed: June 7, 2023
    Publication date: October 5, 2023
    Inventors: Hung-Chun Cho, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
  • Publication number: 20230282558
    Abstract: A package structure includes a first redistribution layer, a semiconductor die and a second redistribution layer. The first redistribution layer includes a first dielectric layer, first conductive elements, second conductive elements, a top dielectric layer and an auxiliary dielectric portion. The first conductive elements and the second conductive elements are disposed on the first dielectric layer with a first pattern density and a second pattern density respectively. The top dielectric layer is disposed on the first dielectric layer and covering a top surface of the second conductive elements. The auxiliary dielectric portion is disposed in between the first dielectric layer and the top dielectric layer, and covering a top surface of the first conductive elements. The semiconductor die is disposed on the first redistribution layer. The second redistribution layer is disposed on the semiconductor die, and electrically connected to the semiconductor die and the first redistribution layer.
    Type: Application
    Filed: March 1, 2022
    Publication date: September 7, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Han Wang, Sih-Hao Liao, Wei-Chih Chen, Hung-Chun Cho, Ting-Chen Tseng, Yu-Hsiang Hu, Hung-Jui Kuo
  • Publication number: 20230260661
    Abstract: The present invention relates to a method and system for augmenting aneurysm learning data for augmenting artificial images formed of various result values calculated from simulation results.
    Type: Application
    Filed: June 23, 2021
    Publication date: August 17, 2023
    Applicants: INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY ERICA CAMPUS, INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Hyeondong YANG, Je Hoon OH, Yong Bae KIM, Kwang-Chun CHO, Jung-Jae KIM
  • Patent number: 11715717
    Abstract: In an embodiment, a device includes: a semiconductor die including a semiconductor material; a through via adjacent the semiconductor die, the through via including a metal; an encapsulant around the through via and the semiconductor die, the encapsulant including a polymer resin; and an adhesion layer between the encapsulant and the through via, the adhesion layer including an adhesive compound having an aromatic compound and an amino group, the amino group bonded to the polymer resin of the encapsulant, the aromatic compound bonded to the metal of the through via, the aromatic compound being chemically inert to the semiconductor material of the semiconductor die.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: August 1, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Chun Cho, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
  • Publication number: 20230215831
    Abstract: In an embodiment, a method includes forming a conductive feature adjacent to a substrate; treating the conductive feature with a protective material, the protective material comprising an inorganic core with an organic coating around the inorganic core, the treating the conductive feature comprising forming a protective layer over the conductive feature; and forming an encapsulant around the conductive feature and the protective layer. In another embodiment, the method further includes, before forming the encapsulant, rinsing the protective layer with water. In another embodiment, the protective layer is selectively formed over the conductive feature.
    Type: Application
    Filed: March 13, 2023
    Publication date: July 6, 2023
    Inventors: Hung-Chun Cho, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao
  • Publication number: 20230187318
    Abstract: A package structure and method of forming the same are provided. The package structure includes a polymer layer, a redistribution layer, a die, and an adhesion promoter layer. The redistribution layer is disposed over the polymer layer. The die is sandwiched between the polymer layer and the redistribution layer. The adhesion promoter layer, an oxide layer, a through via, and an encapsulant are sandwiched between the polymer layer and the redistribution layer. The encapsulant is laterally encapsulates the die. The through via extends through the encapsulant. The adhesion promoter layer and the oxide layer are laterally sandwiched between the through via and the encapsulant. A bottom portion of the encapsulant is longitudinally sandwiched between the adhesion promoter layer and the polymer layer.
    Type: Application
    Filed: February 8, 2023
    Publication date: June 15, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Chun Cho, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Wei-Chih Chen
  • Publication number: 20230154830
    Abstract: A semiconductor device includes a first die, a second die, a first redistribution layer (RDL) structure and a connector. The RDL structure is disposed between the first die and the second die and is electrically connected to the first die and the second die and includes a first polymer layer, a second polymer layer, a first conductive pattern and an adhesion promoter layer. The adhesion promoter layer is between and in direct contact with the second polymer layer and the first conductive pattern. The connector is disposed in the first polymer layer and in direct contact with the second die and the first conductive pattern.
    Type: Application
    Filed: January 5, 2023
    Publication date: May 18, 2023
    Inventors: Hung-Chun Cho, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
  • Patent number: 11605607
    Abstract: In an embodiment, a method includes forming a conductive feature adjacent to a substrate; treating the conductive feature with a protective material, the protective material comprising an inorganic core with an organic coating around the inorganic core, the treating the conductive feature comprising forming a protective layer over the conductive feature; and forming an encapsulant around the conductive feature and the protective layer. In another embodiment, the method further includes, before forming the encapsulant, rinsing the protective layer with water. In another embodiment, the protective layer is selectively formed over the conductive feature.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: March 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Chun Cho, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao
  • Patent number: 11594472
    Abstract: A package structure and method of forming the same are provided. The package structure includes a die, a via, an encapsulant, an adhesion promoter layer, and a polymer layer. The via is laterally aside the die. The encapsulant laterally encapsulates the die and the via. The adhesion promoter layer is sandwiched between the via and the encapsulant. The encapsulant comprises a portion aside the via and under the adhesion promoter layer, and the portion of the encapsulant is sandwiched between the adhesion promoter layer and the polymer layer.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: February 28, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Chun Cho, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Wei-Chih Chen
  • Publication number: 20220392872
    Abstract: A semiconductor package includes a semiconductor die and a redistribution structure. The semiconductor die is laterally surrounded by a molding compound, and the semiconductor die has a conductive pillar and a complex compound sheath sandwiched between the conductive pillar and the molding compound. The redistribution structure is electrically connected with the semiconductor die and comprises a first via portion at a first side of the redistribution structure and a second via portion at a second side of the redistribution structure, and a base angle of the second via portion is greater than a base angle of the first via portion.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 8, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chih Chen, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Hung-Chun Cho