Abstract: The present disclosure relates to a magneto-resistive random access memory (MRAM) cell having an extended upper electrode, and a method of formation. In some embodiments, the MRAM cell has a magnetic tunnel junction (MTJ) arranged over a conductive lower electrode. A conductive upper electrode is arranged over the magnetic tunnel junction. Below the conductive lower electrode is a first conductive via structure in a first dielectric layer. Below the conductive via structure is a discrete conductive jumper structure in a second dielectric layer. A dielectric body of a third dielectric material that is different from the first dielectric material and the second dielectric material extends vertical from the first dielectric layer at least partially into the second dielectric layer.

Abstract: A system for customized document portfolio management. Corresponding methods and user interfaces are provided accordingly for allowing customized document portfolio management. In an preferred embodiment the system includes a document metadata database storing a plurality of documents and meta information thereof, a management server programmed to rule engine, search, security engine and notification engines, and a web server providing an interactive website for displaying documents and allowing creation of a customized portfolio. The customized portfolio management system preferably provides notification on the website, apprising users of changes in the status of their documents. Unique technical identification codes may be used to establish relationships among document.

Abstract: A system for customizing a design portfolio for an IC product. An IP library management server allows IP providers to upload IP libraries and subsequently verify and sort the uploaded IP libraries. A technology document server allows a foundry to upload technology documents and verify and sort the uploaded technology document. A database stores the verified technology documents, IP libraries, and meta information associated therewith. A design portfolio management server provides a terminal user the verified technology documents and IP libraries for creation of a customized design portfolio thereby and further monitoring the customized design portfolio to send notification when the portfolio status changes.

Abstract: A system for customized document portfolio management. Corresponding methods and user interfaces are provided accordingly for allowing customized document portfolio management. In an preferred embodiment the system includes a document metadata database storing a plurality of documents and meta information thereof, a management server programmed to rule engine, search, security engine and notification engines, and a web server providing an interactive website for displaying documents and allowing creation of a customized portfolio. The customized portfolio management system preferably provides notification on the website, apprising users of changes in the status of their documents. Unique technical identification codes may be used to establish relationships among document.

Abstract: A system for customized portfolio management. A method and user interface is provided accordingly, allowing customized portfolio management. In an exemplary embodiment the system comprises a document metadata database storing a plurality of documents and meta information thereof, a management server programmed to rule engine, search, security engine and notification engines, and a Web server providing an interactive website displaying documents, allowing creation of a customized portfolio. The customized portfolio management system provides notification on the website, apprising users of changes in the status of their documents.

Abstract: A system for customizing a design portfolio for an IC product. An IP library management server allows IP providers to upload IP libraries and subsequently verify and sort the uploaded IP libraries. A technology document server allows a foundry to upload technology documents and verify and sort the uploaded technology document. A database stores the verified technology documents, IP libraries, and meta information associated therewith. A design portfolio management server provides a terminal user the verified technology documents and IP libraries for creation of a customized design portfolio thereby and further monitoring the customized design portfolio to send notification when the portfolio status changes.

Abstract: A die seal structure having trenches is provided. The die seal structure is formed on a silicon substrate and used to prevent lateral stress from causing damage to internal circuits in a die when a wafer is being cutted. A die seal comprises a buffer area, a seal ring and a buffer space. The buffer area is adjacent to the internal circuit. The buffer space is adjacent to a scribe line. The seal ring having a structure of stacked metal layers and dielectric layers is located between the buffer area and the buffer space. A trench for enhancing the stress-protection ability of the die seal is formed in the buffer space. The trench is formed by wet-etching SiO2 residues on the buffer space using buffered HF, or wet-etching Si3N4 residues on the buffer space using phosphoric acid at 180° C. In addition, a portion of the substrate may be removed by wet etching using HNO3 and HF. Dry etching may also be used to remove the dielectric residues and a portion of the silicon substrate on the buffer space.

Abstract: A method of manufacturing self-aligned titanium salicide is provided which includes the steps of forming a LOCOS isolation region on a silicon substrate, forming a titanium layer on the surface of the silicon substrate, performing a first two-step rapid thermal anneal on the silicon substrate in an ambient filled with hydrogen and nitrogen gases to convert the titanium layer into a titanium salicide layer, selectively etching the silicon substrate to remove the titanium layer that has not reacted with the silicon substrate, and performing a second two-step rapid thermal anneal on the silicon substrate in an ambient filled with hydrogen and nitrogen gases. Each of the two-step rapid thermal anneals include a first pre-heat step and a second anneal step.

Abstract: A two-step metal salicide semiconductor process, suitable for a semiconductor substrate on which gates, sources (drains), spacers, and field oxides are formed. A first metal layer is formed on the gates. A first high-temperature process is executed to form a first metal salicide layer on the gates. A second metal layer is formed on the first metal salicide layer, sources (drains), spacers, and field oxides. A second high-temperature process is executed to form a thicker second metal salicide layer on the gates and a third metal salicide layer on the sources (drains). A wet etching is then performed. A dielectric layer is formded over the semiconductor substrate wherein the horizontal line of the dielectric layer is above the second metal salicide layer. Polishing is then performed. Finally, shallow contact windows and deep contact windows are then formed for the gates and sources (drains), respectively.

Abstract: The present invention provides a method of fabricating a die seal. The die seal comprises a buffer area being adjacent to a die, a buffer space being adjacent to a scribe line, and a seal ring located between the buffer area and the buffer space. The seal ring is stacked by at least one metal layer and at least one dielectric layer. A passivation layer is formed and covers entire the die seal. The method comprises forming an amorphous silicon film on a top metal layer prior to the step of forming the passivation layer, and removing the dielectric layer on the buffer space by applying the amorphous silicon film as an etch stop layer in the step of etching the passivation layer to enhance the robustness of the die seal from damage by a lateral stress when a wafer is sawed. When the dielectric layer is made of SiO.sub.2, a plasma containing CF.sub.4 and H.sub.2. can be utilized in the step of etching the passivation layer. Because the plasma has an extremely high etching selectivity ratio, the SiO.sub.

Abstract: A method for improving the electrical property of gate in polycide structure is disclosed. First, a gate oxide layer is formed on the surface of the silicon substrate. The following procedure acts as one of the key points for the invention comprising the process steps of (1) forming a highly-doped polysilicon layer on the gate oxide, (2) forming an undoped amorphous silicon layer on the polysilicon layer, and followed by (3) forming a tungsten silicon layer on the amorphous silicon. Next, annealing at high temperature and in short time is performed. Such a stacked gate structure has low resistance and can solve the following problems: (1)peeling of tungsten silicide after annealing, (2) degradation of the electrical property of gate due to the diffusing and penetration of fluorine atoms coming from tungsten silicide.

Abstract: A mask structure for etching contacts and its method of use. The mask structure includes: a support glass; a layer of chromium, which blocks the light completely; a layer of partial light shielding material, which determines how much light is to be transmitted by its thickness; a first contact pattern; and a second contact pattern. The first contact pattern allows full light transmission while the second contact pattern allows partial light transmission.

Abstract: A method for forming a gate-side air-gap structure in a salicide process for preventing bridging, which starts on a semiconductor wafer with active region defined completely by field oxide, includes the steps: depositing sequentially a thin oxide layer, a polysilicon layer, and a first layer over the wafer; patterning the first layer, the polysilicon layer, and the thin oxide layer to form a stack gate which consists of first layer and a gate, wherein the gate consists of the polysilicon layer and the thin oxide layer; forming lightly-doped drains beside the stack gate in the active region; forming a second layer on the sidewall of the stack gate; forming a spacer on the sidewall of the second layer; forming source and drain regions; removing the first layer and the second layer to reveal the gate, wherein air gaps exist between the gate and the spacer; depositing a titanium layer over the wafer; heating the titanium layer to form TiSi.sub.