Patents by Inventor Chun-Chung Ko

Chun-Chung Ko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor structure for electrostatic discharge protection
    Patent number: 9293424
    Abstract: A semiconductor structure is arranged on an integrated circuit, the integrated circuit includes a seal ring arranged at outer periphery of the integrated circuit, a metal ring arranged at an inner side of the seal ring and a power bus arranged at a side of the metal ring. The semiconductor structure includes a first P type electrode area, a second P type electrode area and a first N type electrode area. The first P type electrode area is formed at a position on a P well corresponding to the seal ring, and coupled to the seal ring. The second P type electrode area is formed at a position on the P well corresponding to the metal ring, and coupled to the metal ring. The first N type electrode area is formed at a position corresponding to the power bus, and coupled to the power bus.
    Type: Grant
    Filed: October 12, 2014
    Date of Patent: March 22, 2016
    Assignee: Advanced Analog Technology, Inc.
    Inventors: Chun-Chung Ko, Chih-Lun Wu, Shuo-Yen Lin
  • Semiconductor structure for electrostatic discharge protection
    Patent number: 9202807
    Abstract: A semiconductor structure includes a P well formed on a P type substrate; a first N type electrode area formed on a central region of the P well; a first insulating area formed on the P well and surrounding the first N type electrode area; a second N type electrode area formed on the P well and surrounding the first insulating area; a second insulating area formed on the P well and surrounding the second N type electrode area; and a P type electrode area formed on the P well and surrounding the second insulating area; wherein periphery outlines of the first N type electrode area and the second N type electrode area are both 8K sided polygons or circles, and K is a positive integer.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: December 1, 2015
    Assignee: Advanced Analog Technology, Inc.
    Inventors: Chun-Chung Ko, Chih-Lun Wu, Shuo-Yen Lin
  • SEMICONDUCTOR STRUCTURE FOR ELECTROSTATIC DISCHARGE PROTECTION
    Publication number: 20150179629
    Abstract: A semiconductor structure includes a P well formed on a P type substrate; a first N type electrode area formed on a central region of the P well; a first insulating area formed on the P well and surrounding the first N type electrode area; a second N type electrode area formed on the P well and surrounding the first insulating area; a second insulating area formed on the P well and surrounding the second N type electrode area; and a P type electrode area formed on the P well and surrounding the second insulating area; wherein periphery outlines of the first N type electrode area and the second N type electrode area are both 8K sided polygons or circles, and K is a positive integer.
    Type: Application
    Filed: June 17, 2014
    Publication date: June 25, 2015
    Inventors: Chun-Chung Ko, Chih-Lun Wu, Shuo-Yen Lin
  • SEMICONDUCTOR STRUCTURE FOR ELECTROSTATIC DISCHARGE PROTECTION
    Publication number: 20150179628
    Abstract: A semiconductor structure is arranged on an integrated circuit, the integrated circuit includes a seal ring arranged at outer periphery of the integrated circuit, a metal ring arranged at an inner side of the seal ring and a power bus arranged at a side of the metal ring. The semiconductor structure includes a first P type electrode area, a second P type electrode area and a first N type electrode area. The first P type electrode area is formed at a position on a P well corresponding to the seal ring, and coupled to the seal ring. The second P type electrode area is formed at a position on the P well corresponding to the metal ring, and coupled to the metal ring. The first N type electrode area is formed at a position corresponding to the power bus, and coupled to the power bus.
    Type: Application
    Filed: October 12, 2014
    Publication date: June 25, 2015
    Inventors: Chun-Chung Ko, Chih-Lun Wu, Shuo-Yen Lin