Abstract: A shift register including a voltage set unit, a driver unit, a control unit, a first transistor, a second transistor, a third transistor and a fourth transistor is provided. The voltage set unit provides a terminal voltage. The driver unit provides a main gate signal according to the terminal voltage and a clock signal. The control unit provides a control signal. The first transistor receives the terminal voltage, a level reference voltage and the control signal. The second transistor is coupled to the first transistor and receives a low voltage and the control signal. The third transistor receives the terminal voltage, a level reference voltage and a gate reference signal. The fourth transistor is coupled to the third transistor and receives the low voltage and the gate reference signal.

Abstract: A shift register including a voltage set unit, a driver unit, a control unit, a first transistor, a second transistor, a third transistor and a fourth transistor is provided. The voltage set unit provides a terminal voltage. The driver unit provides a main gate signal according to the terminal voltage and a clock signal. The control unit provides a control signal. The first transistor receives the terminal voltage, a level reference voltage and the control signal. The second transistor is coupled to the first transistor and receives a low voltage and the control signal. The third transistor receives the terminal voltage, a level reference voltage and a gate reference signal. The fourth transistor is coupled to the third transistor and receives the low voltage and the gate reference signal.

Abstract: A touch display apparatus includes a touch driver and a display driver. The touch driver outputs touch signals to drive a touch panel. The display driver outputs scan signals to drive a display panel. A display driver has a plurality of shift registers, and each of the plurality of shift registers includes a pull-up unit, a driving unit, a pull-down unit and a holding unit. The pull-up unit is electrically connected to a driving node for outputting a driving voltage. The driving unit is electrically connected to the driving node for outputting a first scan signal according to a clock. A pull-down unit is electrically connected to the driving node and the output terminal, for pulling down the voltage level of the driving voltage and the first scan signal, respectively. The holding unit is electrically connected to the driving node.

Abstract: A driving circuit comprises a plurality of shift register (SR). An ith SR among the plurality SR's comprises a resetting circuit, an input switch, a capacitor, and an output circuit. The resetting circuit is used for adjusting a resetting voltage according to a control voltage. The input switch is used for adjusting the control voltage according to an (i?2)th driving signal from an (i?2)th SR among the plurality of SR's, selectively. The capacitor is used for adding a voltage variation of a boosting signal to the control voltage. The output circuit is used for taking an ith input signal as an ith output signal according to the control voltage and the resetting voltage, selectively. The positive edge of the boosting voltage leads the negative edge of the ith input signal.

Abstract: A touch display apparatus includes a touch driver and a display driver. The touch driver outputs touch signals to drive a touch panel. The display driver outputs scan signals to drive a display panel. A display driver has a plurality of shift registers, and each of the plurality of shift registers includes a pull-up unit, a driving unit, a pull-down unit and a holding unit. The pull-up unit is electrically connected to a driving node for outputting a driving voltage. The driving unit is electrically connected to the driving node for outputting a first scan signal according to a clock. A pull-down unit is electrically connected to the driving node and the output terminal, for pulling down the voltage level of the driving voltage and the first scan signal, respectively. The holding unit is electrically connected to the driving node.

Abstract: A display panel includes gate lines and a gate driver. The gate driver includes series coupled driving stages, in which an N-th driving stage of the series-coupled driving stages includes a driving unit and an input control unit. The driving unit transmits a first clock signal according to a control voltage level of a control node, so as to output a gate-driving signal. The input control unit transmits the gate-driving signal outputted from an (N?1)-th driving stage to the control nodes, so as to adjust the control voltage level to one of a first voltage level and a second voltage level. A predetermined time interval is present between a rising edge of the first clock signal and a falling edge of the second clock signal. During the predetermined time interval, the control voltage level is pulled to the first voltage level by the input control unit.

Abstract: A driving circuit comprises a plurality of shift register (SR). An ith SR among the plurality SR's comprises a resetting circuit, an input switch, a capacitor, and an output circuit. The resetting circuit is used for adjusting a resetting voltage according to a control voltage. The input switch is used for adjusting the control voltage according to an (i?2)th driving signal from an (i?2)th SR among the plurality of SR's, selectively. The capacitor is used for adding a voltage variation of a boosting signal to the control voltage. The output circuit is used for taking an ith input signal as an ith output signal according to the control voltage and the resetting voltage, selectively. The positive edge of the boosting voltage leads the negative edge of the ith input signal.

Abstract: A display panel includes gate lines and a gate driver. The gate driver includes series coupled driving stages, in which an N-th driving stage of the series-coupled driving stages includes a driving unit and an input control unit. The driving unit transmits a first clock signal according to a control voltage level of a control node, so as to output a gate-driving signal. The input control unit transmits the gate-driving signal outputted from an (N?1)-th driving stage to the control nodes, so as to adjust the control voltage level to one of a first voltage level and a second voltage level. A predetermined time interval is present between a rising edge of the first clock signal and a falling edge of the second clock signal. During the predetermined time interval, the control voltage level is pulled to the first voltage level by the input control unit.

Abstract: A driving circuit comprises a plurality of shift register (SR). An ith SR among the plurality SR's comprises a resetting circuit, an input switch, a capacitor, and an output circuit. The resetting circuit is used for adjusting a resetting voltage according to a control voltage. The input switch is used for adjusting the control voltage according to an (i?2)th driving signal from an (i?2)th SR among the plurality of SR's, selectively. The capacitor is used for adding a voltage variation of a boosting signal to the control voltage. The output circuit is used for taking an ith input signal as an ith output signal according to the control voltage and the resetting voltage, selectively. The positive edge of the boosting voltage leads the negative edge of the ith input signal.

Abstract: A driving circuit comprises a plurality of shift register (SR). An ith SR among the plurality SR's comprises a resetting circuit, an input switch, a capacitor, and an output circuit. The resetting circuit is used for adjusting a resetting voltage according to a control voltage. The input switch is used for adjusting the control voltage according to an (i?2)th driving signal from an (i?2)th SR among the plurality of SR's, selectively. The capacitor is used for adding a voltage variation of a boosting signal to the control voltage. The output circuit is used for taking an ith input signal as an ith output signal according to the control voltage and the resetting voltage, selectively. The positive edge of the boosting voltage leads the negative edge of the ith input signal.

Abstract: A pixel circuit of a liquid crystal display (LCD) has a first switch, a second switch, a third switch, a storage capacitor and a liquid crystal capacitor. The first switch controls electrical connection between a data line and the storage capacitor according to a voltage level of a first gate line. The second switch controls electrical connection between the storage capacitor and the liquid crystal capacitor according to a voltage level of a second gate line. The third switch controls electrical connection between a bias line and the liquid crystal capacitor according to the voltage level of the first gate line. Within each frame period of the LCD, the second switch is turned off while the first switch and the third switch are turned on, and the first switch and the third switch are turned off while the second switch is turned on.

Abstract: A display includes a scan line, a data line, a pixel circuit, a compensation circuit, a voltage controller, and a data line driver. The data line forms a junction with the scan line. The pixel circuit is disposed at the junction of the scan line and the data line. When the scan line and the data line are driven, the pixel circuit generates a driving current. The compensation circuit generates a comparing signal and a positioning signal based on the driving current. The voltage controller generates a reference voltage that corresponds to the positioning signal with reference to the comparing signal. The data line driver corrects an image signal based on the reference voltage, and drives the data line with the corrected image signal. A compensation circuit for the display is also disclosed.

Abstract: A shift register includes a plurality of electrically connected shift units. Each shift unit includes a pull-up circuit, a pull-up driving circuit, a pull-down circuit, and a pull-down driving circuit. The pull-up circuit outputs a first signal to an output node according to the first signal and a voltage of a driving node. The pull-up driving drives the pull-up circuit according to an output voltage of the previous shift unit. The pull-down driving circuit outputs a low level voltage to the driving node and the output node according to the first signal and a second signal. The pull-down circuit resets the pull-up driving circuit according to the voltage of the output node and outputs the low level voltage to the output node and the driving node according to a third signal and a fourth signal.

Abstract: A display includes a scan line, a data line, a pixel circuit, a compensation circuit, a voltage controller, and a data line driver. The data line forms a junction with the scan line. The pixel circuit is disposed at the junction of the scan line and the data line. When the scan line and the data line are driven, the pixel circuit generates a driving current. The compensation circuit generates a comparing signal and a positioning signal based on the driving current. The voltage controller generates a reference voltage that corresponds to the positioning signal with reference to the comparing signal. The data line driver corrects an image signal based on the reference voltage, and drives the data line with the corrected image signal. A compensation circuit for the display is also disclosed.

Abstract: A shift register includes a plurality of shift register stages for providing gate signals. Each shift register stage has a pull-up unit, a carry unit, a carry control unit, an input unit and a pull-down unit. The pull-up unit is employed to pull up a gate signal according to a driving control voltage and a first clock. The carry unit generates a preliminary start pulse signal based on the driving control voltage and the first clock. The carry control unit outputs the preliminary start pulse signal to become a forward or backward start pulse signal according to first and second bias voltages. The input unit is utilized for inputting a start pulse signal generated by a preceding or succeeding shift register stage to become the driving control voltage. The pull-down unit pulls down the gate signal, the preliminary start pulse signal and the driving control voltage according to multiple clocks.

Abstract: A shift register includes a plurality of electrically connected shift units. Each shift unit includes a pull-up circuit, a pull-up driving circuit, a pull-down circuit, and a pull-down driving circuit. The pull-up circuit outputs a first signal to an output node according to the first signal and a voltage of a driving node. The pull-up driving drives the pull-up circuit according to an output voltage of the previous shift unit. The pull-down driving circuit outputs a low level voltage to the driving node and the output node according to the first signal and a second signal. The pull-down circuit resets the pull-up driving circuit according to the voltage of the output node and outputs the low level voltage to the output node and the driving node according to a third signal and a fourth signal.

Abstract: A shift register includes a plurality of shift register stages for providing gate signals. Each shift register stage has a pull-up unit, a carry unit, a carry control unit, an input unit and a pull-down unit. The pull-up unit is employed to pull up a gate signal according to a driving control voltage and a first clock. The carry unit generates a preliminary start pulse signal based on the driving control voltage and the first clock. The carry control unit outputs the preliminary start pulse signal to become a forward or backward start pulse signal according to first and second bias voltages. The input unit is utilized for inputting a start pulse signal generated by a preceding or succeeding shift register stage to become the driving control voltage. The pull-down unit pulls down the gate signal, the preliminary start pulse signal and the driving control voltage according to multiple clocks.