Abstract: A fin field effect transistor (FinFET) device structure is provided. The FinFET device structure includes a plurality of fin structures above a substrate, an isolation structure over the substrate and between the fin structures, and a gate structure formed over the fin structure. The FinFET device structure includes a source/drain (S/D) structure over the fin structure, and the S/D structure is adjacent to the gate structure. The FinFET device structure also includes a metal silicide layer over the S/D structure, and the metal silicide layer is in contact with the isolation structure.

Abstract: One or more values associated with a first configuration setting for a first circuit may be stored in a first set of one or more registers when an operation of the first circuit is based at least in part on one or more values associated with a second configuration setting stored in a second set of one or more registers. In response to receiving an indication of a change in an operating frequency or voltage of the first circuit, the one or more values stored in the second set of one or more registers may be changed by loading the one or more values associated with the first configuration setting stored in the first set of one or more registers into the second set of one or more registers in a parallel fashion.

Abstract: A multi-channel memory system has a memory device, a plurality of channels, and a control circuit. The memory device has a plurality of memory storage spaces. The channels are coupled to the memory storage spaces, respectively, wherein each of the channels is configured to act as a memory interface for accessing a corresponding memory storage space independently. The control circuit controls clock frequencies of clocks on the channels, respectively. At a same time point, the channels include at least a first channel operating at a first clock frequency set by the control circuit and a second channel operating at a second clock frequency set by the control circuit at a same time point, and the second clock frequency is different from the first clock frequency.

Abstract: A multi-channel memory system has a memory device, a plurality of channels, and a control circuit. The memory device has a plurality of memory storage spaces. The channels are coupled to the memory storage spaces, respectively, wherein each of the channels is configured to act as a memory interface for accessing a corresponding memory storage space independently. The control circuit controls clock frequencies of clocks on the channels, respectively. At a same time point, the channels include at least a first channel operating at a first clock frequency set by the control circuit and a second channel operating at a second clock frequency set by the control circuit at a same time point, and the second clock frequency is different from the first clock frequency.

Abstract: One or more values associated with a first configuration setting for a first circuit may be stored in a first set of one or more registers when an operation of the first circuit is based at least in part on one or more values associated with a second configuration setting stored in a second set of one or more registers. In response to receiving an indication of a change in an operating frequency or voltage of the first circuit, the one or more values stored in the second set of one or more registers may be changed by loading the one or more values associated with the first configuration setting stored in the first set of one or more registers into the second set of one or more registers in a parallel fashion.

Abstract: An integrated circuit has a semiconductor layer, at least one metal layer, a plurality of functional circuit blocks formed on the semiconductor layer, and a power mesh formed on the at least one metal layer. The power mesh has a specific area corresponding to a specific functional circuit block of the functional circuit blocks. The specific area at least has a first power trunk of a first power source and a second power trunk of a second power source distributed therein.