Abstract: An acute kidney injury predicting system and a method thereof are proposed. A processor reads the data to be tested, the detection data, the machine learning algorithm and the risk probability comparison table from a main memory. The processor trains the detection data according to the machine learning algorithm to generate an acute kidney injury prediction model, and inputs the data to be tested into the acute kidney injury prediction model to generate an acute kidney injury characteristic risk probability and a data sequence table. The data sequence table lists the data to be tested in sequence according to a proportion of each of the data to be tested in the acute kidney injury characteristics. The processor selects one of the medical treatment data from the risk probability comparison table according to the acute kidney injury characteristic risk probability.

Abstract: A device for encouraging and guiding a spirometer user includes a housing, a main valve, a visual assembly, and a sound making assembly. The housing has a guiding channel, a first outlet channel, a second outlet channel, and an inlet channel. The main valve is disposed in a housing communicating with the guiding channel, the first outlet channel, the second outlet channel or the inlet channel and configured to regulate or control fluid flowing paths. The visual assembly includes a check valve in the second outlet channel, and at least one movable member. The sound making assembly includes a check valve and a sound maker. So, it can generate the visual and sound encouraging effects for learning how to use a spirometer correctly.

Abstract: The present disclosure provides a multi-state one-time programmable (MSOTP) memory circuit including a memory cell and a programming voltage driving circuit. The memory cell includes a MOS storage transistor, a first MOS access transistor and a second MOS access transistor electrically connected to store two bits of data. When the memory cell is in a writing state, the programming voltage driving circuit outputs a writing control potential to the gate of the MOS storage transistor, and when the memory cell is in a reading state, the programming voltage driving circuit outputs a reading control potential to the gate of the MOS storage transistor.

Abstract: A skateboard includes a deck, at least a front wheel set and a rear wheel set. The front wheel set, which is arranged at a bottom of the deck at a position close to a front end thereof, includes at least one rigid and rotatable front wheel frame and at least two front wheels. The rear wheel set, which is arranged at a bottom of the deck at a position close to the rear end thereof, includes at least one rigid and non-rotatable rear wheel frame and at least two rear wheels. The outer side of the wheel is circular or arc-shaped. The structure of the skateboard allows the user to change a center of gravity and to lift the sides of the board with foot, so as to only rely on the outer arc of the left or right front and rear wheels to slide, while the rotatable front wheel frame in the left or right side may still be utilized for rotating in the forward direction, which allows a skateboard experience of forward or changing the travelling direction.

Abstract: Disclosed is a memory device and an operation method thereof. The operation method of memory device, comprising: programming a plurality of sub-matrices including at least one of non-zero element of a rearranged matrix to a plurality of operation units of the memory device; and programming a mapping table into a working memory of a memory device. The rearranged matrix is generated by rearrange a plurality of columns and a plurality of rows of an original matrix according to the positions of a plurality of non-zero elements of the original matrix. The mapping table comprises a correspondence of row indexes between the original matrix and the rearranged matrix, a correspondence of column indexes between the original matrix and the rearranged matrix and a correspondence between the sub-matrices including at least one non-zero element and the operation units storing the sub-matrices including at least one non-zero element.

Abstract: A method for neural network computation using adaptive data representation, adapted for a processor to perform multiply-and-accumulate operations on a memory having a crossbar architecture, is provided. The memory comprises multiple input and output lines crossing each other, multiple cells respectively disposed at intersections of the input and output lines, and multiple sense amplifiers respectively connected to the output lines. In the method, an input cycle of kth bits respectively in an input data is adaptively divided into multiple sub-cycles, wherein a number of the divided sub-cycles is determined according to a value of k. The kth bits of the input data are inputted to the input lines with the sub-cycles and computation results of the output lines are sensed by the sense amplifiers. The computation results sensed in each sub-cycle are combined to obtain the output data corresponding to the kth bits of the input data.

Abstract: A method for neural network computation using adaptive data representation, adapted for a processor to perform multiply-and-accumulate operations on a memory having a crossbar architecture, is provided. The memory comprises multiple input and output lines crossing each other, multiple cells respectively disposed at intersections of the input and output lines, and multiple sense amplifiers respectively connected to the output lines. In the method, an input cycle of kth bits respectively in an input data is adaptively divided into multiple sub-cycles, wherein a number of the divided sub-cycles is determined according to a value of k. The kth bits of the input data are inputted to the input lines with the sub-cycles and computation results of the output lines are sensed by the sense amplifiers. The computation results sensed in each sub-cycle are combined to obtain the output data corresponding to the kth bits of the input data.

Abstract: A method and an apparatus for neural network computation using adaptive data representation, adapted for a processor to perform multiply-and-accumulate operations on a memory having a crossbar architecture, are provided. The memory comprises multiple input and output lines crossing each other, multiple cells respectively disposed at intersections of the input and output lines, and multiple sense amplifiers respectively connected to the output lines. In the method, an input cycle of kth bits respectively in an input data is adaptively divided into multiple sub-cycles, wherein a number of the divided sub-cycles is determined according to a value of k. The kth bits of the input data are inputted to the input lines with the sub-cycles and computation results of the output lines are sensed by the sense amplifiers. The computation results sensed in each sub-cycle are combined to obtain the output data corresponding to the kth bits of the input data.

Abstract: A skateboard includes a deck, at least a front wheel set and a rear wheel set. The front wheel set, which is arranged at a bottom of the deck at a position close to a front end thereof, includes at least one rigid and rotatable front wheel frame and at least two front wheels. The rear wheel set, which is arranged at a bottom of the deck at a position close to the rear end thereof, includes at least one rigid and non-rotatable rear wheel frame and at least two rear wheels. The outer side of the wheel is circular or arc-shaped. The structure of the skateboard allows the user to change a center of gravity and to lift the sides of the board with foot, so as to only rely on the outer arc of the left or right front and rear wheels to slide, while the rotatable front wheel frame in the left or right side may still be utilized for rotating in the forward direction, which allows a skateboard experience of forward or changing the travelling direction.

Abstract: Disclosed is a memory device and an operation method thereof. The operation method of memory device, comprising: programming a plurality of sub-matrices including at least one of non-zero element of a rearranged matrix to a plurality of operation units of the memory device; and programming a mapping table into a working memory of a memory device. The rearranged matrix is generated by rearrange a plurality of columns and a plurality of rows of an original matrix according to the positions of a plurality of non-zero elements of the original matrix. The mapping table comprises a correspondence of row indexes between the original matrix and the rearranged matrix, a correspondence of column indexes between the original matrix and the rearranged matrix and a correspondence between the sub-matrices including at least one non-zero element and the operation units storing the sub-matrices including at least one non-zero element.

Abstract: Methods, computer program products, and systems are presented. There can be provided for example: obtaining user defined connectivity pattern information; and establishing commands for provisioning one or more network device for implementation of a network connection based on the user defined connectivity pattern information.

Abstract: A method and an apparatus for neural network computation using adaptive data representation, adapted for a processor to perform multiply-and-accumulate operations on a memory having a crossbar architecture, are provided. The memory comprises multiple input and output lines crossing each other, multiple cells respectively disposed at intersections of the input and output lines, and multiple sense amplifiers respectively connected to the output lines. In the method, an input cycle of kth bits respectively in an input data is adaptively divided into multiple sub-cycles, wherein a number of the divided sub-cycles is determined according to a value of k. The kth bits of the input data are inputted to the input lines with the sub-cycles and computation results of the output lines are sensed by the sense amplifiers. The computation results sensed in each sub-cycle are combined to obtain the output data corresponding to the kth bits of the input data.

Abstract: Methods, computer program products, and systems are presented. There can be provided for example: obtaining user defined connectivity pattern information; and establishing commands for provisioning one or more network device for implementation of a network connection based on the user defined connectivity pattern information.

Abstract: Methods, computer program products, and systems are presented. There can be provided for example: obtaining user defined connectivity pattern information; and establishing commands for provisioning one or more network device for implementation of a network connection based on the user defined connectivity pattern information.

Abstract: Methods, computer program products, and systems are presented. There can be provided for example: obtaining user defined connectivity pattern information; and establishing commands for provisioning one or more network device for implementation of a network connection based on the user defined connectivity pattern information.

Abstract: An approach for querying and managing/manipulating network computing resources (e.g., cloud computing resources) is provided. Typically, an interpreter component may be implemented so that a language describing such computing resources may be interpreted. The interpreter component may include other components such as a request processor, a provisioning queue, an execution engine, a results store, and response marshaller/handler that collaborate to manage the computing resources. Such computing resources may, for example, include virtual machine instances, virtual machine images, storage volumes, network resources, files, software bundles, etc.

Abstract: An approach for querying and managing/manipulating network computing resources (e.g., cloud computing resources) is provided. Typically, an interpreter component may be implemented so that a language describing such computing resources may be interpreted. The interpreter component may include other components such as a request processor, a provisioning queue, an execution engine, a results store, and response marshaller/handler that collaborate to manage the computing resources. Such computing resources may, for example, include virtual machine instances, virtual machine images, storage volumes, network resources, files, software bundles, etc.

Abstract: A multi-stream voice transmission system includes a transmitting terminal and a receiving terminal for transmitting and receiving first and second packet streams via first and second network channels. The receiving terminal includes a playout buffer for buffering the first and second packet streams, generates an output voice signal from the buffered packets according to a playout schedule adjusting coefficient ?, generates packet loss parameters and packet delay parameters corresponding to loss and delay experienced by the first and second packet streams, and provides the parameters to the transmitting terminal.

Abstract: A waste tire pulverizing and separation machine including a machine body, and a roll-in mechanism, a pulverizing barrel, and a separation conveyer accommodated in the machine body. The roll-in mechanism is mounted at an input side at an upper side of the machine body and is comprised of an upper roller assembly and a lower roller assembly. Each roller assembly comprises a plurality of rollers arranged in a row. Each roller is provided with ratchet wheels and are driven to synchronously rotate by a motor via chains. The pulverizing barrel is mounted at a rear side of an output end of the roll-in mechanism. A circumferential surface of the pulverizing barrel is provided with a plurality of alternately arranged cutters. A curved sieve is located below the pulverizing barrel. The separation conveyer is disposed below the pulverizing barrel and comprised of a plurality of rollers mounted between two frames. An output roller at an output end of the separation conveyer is provided with a magnetic tape.