Abstract: A farming machine including a number of treatment mechanisms treats plants according to a treatment plan as the farming machine moves through the field. The control system of the farming machine executes a plant identification model configured to identify plants in the field for treatment. The control system generates a treatment map identifying which treatment mechanisms to actuate to treat the plants in the field. To generate a treatment map, the farming machine captures an image of plants, processes the image to identify plants, and generates a treatment map. The plant identification model can be a convolutional neural network having an input layer, an identification layer, and an output layer. The input layer has the dimensionality of the image, the identification layer has a greatly reduced dimensionality, and the output layer has the dimensionality of the treatment mechanisms.

Abstract: The present disclosure describes a method of patterning a semiconductor wafer using extreme ultraviolet lithography (EUVL). The method includes receiving an EUVL mask that includes a substrate having a low temperature expansion material, a reflective multilayer over the substrate, a capping layer over the reflective multilayer, and an absorber layer over the capping layer. The method further includes patterning the absorber layer to form a trench on the EUVL mask, wherein the trench has a first width above a target width. The method further includes treating the EUVL mask with oxygen plasma to reduce the trench to a second width, wherein the second width is below the target width. The method may also include treating the EUVL mask with nitrogen plasma to protect the capping layer, wherein the treating of the EUVL mask with the nitrogen plasma expands the trench to a third width at the target width.

Abstract: A method for manufacturing a semiconductor structure includes forming a semiconductor portion which has an exposed region; forming two fin sidewalls which are disposed at two opposite sides of the exposed region of the semiconductor portion, and which include a dielectric material; and performing an etching process such that the exposed region of the semiconductor portion is etched away to form a recess while a protection layer is formed to protect each of the fin sidewalls during the etching process. Other methods for manufacturing the semiconductor structure are also disclosed.

Abstract: A method for processing an integrated circuit includes forming a plurality of transistors. The method utilizes a reversed tone patterning process to selectively drive dipoles into the gate dielectric layers of some of the transistors while preventing dipoles from entering the gate dielectric layers of other transistors. This process can be repeated to produce a plurality of transistors each having different threshold voltages.

Abstract: An immersion cooling tank includes a tank body and a liquid flow tube. The tank body holds a coolant and an electronic device. The tank body defines an inlet and an outlet. The inlet and the outlet are respectively located at opposite ends of the electronic device for inputting and outputting the coolant. The coolant flows through the electronic device. The liquid flow tube includes at least one adjuster. The liquid flow tube is located inside the tank body and coupled to at least one of the inlet or the outlet. The at least one adjuster faces the electronic device for controlling an amount of the coolant flowing in or out of the tank body.

Abstract: The present disclosure provides a semiconductor device that includes channel layers vertically stacked over a substrate, a gate structure engaging the channel layers, a source/drain (S/D) formation assistance region partially embedded in the substrate and under a bottommost one of the channel layers, and an S/D epitaxial feature interfacing both the S/D formation assistance region and lateral ends of the channel layers. The S/D formation assistance region includes a semiconductor seed layer embedded in an isolation layer. The isolation layer separates the semiconductor seed layer from physically contacting the substrate.

Abstract: A semiconductor memory device includes a stack of alternating insulating layers and first conductive layers disposed over a substrate; a plurality of memory cell strings penetrating the stack over the substrate, each memory cell string comprising a central portion extending through the stack, a semiconductor layer surrounding the central portion, and a ferroelectric layer surrounding the semiconductor layer, and the central portion comprising a channel isolation structure and a second conductive layer and a third conductive layer at two sides of the channel isolation structure; and a plurality of cell isolation structures penetrating the conductive layers and the insulating layers over the substrate and disposed between two memory cell strings, each cell isolation structure comprising a top portion and a bottom portion adjoined to the top portion and different from the top portion.

Abstract: A method includes adding a first additive to an electroplating solution, wherein the first additive is a relatively weak suppressing agent; adding a second additive to the electroplating solution, wherein the second additive is a relatively strong suppressing agent; adding a third additive to the electroplating solution, wherein the third additive is a leveling agent; and depositing copper using the electroplating solution, wherein most of the copper is nanotwinned grains having a (111)-orientation.

Abstract: A method of forming a semiconductor device includes forming a first dielectric layer over a first channel region in a first region and over a second channel region in a second region; introducing a first dipole element into the first dielectric layer in the first region to form a first dipole-containing gate dielectric layer in the first region; forming a second dielectric layer over the first dipole-containing gate dielectric layer; introducing fluorine into the second dielectric layer to form a first fluorine-containing gate dielectric layer over the first dipole-containing gate dielectric layer; and forming a gate electrode over the first fluorine-containing gate dielectric layer.

Abstract: A cooling method for controlling a cooling system to cool a data center, the cooling system includes a chiller unit, a cooling tower, and at least one cooling water storage tank, the method includes determining whether the cooling system is under a first condition, a second condition, or a third condition; when the cooling system is under the first condition, controlling the chiller unit to provide cooling water to the data center; when the cooling system is under the second condition, controlling the chiller unit to provide cooling water to the data center and the at least one cooling water storage tank; and when the cooling system is under the third condition, controlling the at least one cooling water storage tank to provide cooling water to the data center and the chiller unit to refill cooling water to the at least one cooling water storage tank.

Abstract: A high-speed connector includes an insulating housing, a first terminal assembly received in the insulating housing, a second terminal assembly received in the insulating housing, a third terminal assembly received in the insulating housing, and a fourth terminal assembly received in the insulating housing. The second terminal assembly is opposite to the first terminal assembly along an up-down direction. The third terminal assembly is disposed between the first terminal assembly and the second terminal assembly. The fourth terminal assembly is corresponding to the third terminal assembly. The fourth terminal assembly is disposed between the second terminal assembly and the third terminal assembly.

Abstract: A semiconductor device structure and methods of forming the same are described. The structure includes a gate dielectric layer disposed over a substrate, a gate electrode layer disposed over the gate dielectric layer, and a first gate spacer disposed adjacent the gate dielectric layer, wherein the first gate spacer comprises an inner surface facing the gate dielectric layer and an outer surface opposite the inner surface, and the first gate spacer includes an oxygen concentration that decreases from the inner surface towards the outer surface of the first gate spacer.

Abstract: A backlight module includes a reflective plate, a plurality of light-emitting elements and a plurality of light guide plates. The reflective plate has light source grooves and first position limiting parts, and each light source groove has a reflective surface, a light outlet and a bottom side. The reflective surface is located between the light outlet and the bottom side. The first position limiting parts are respectively connected to the reflective surfaces and are respectively close to the light outlets. The light-emitting elements are respectively disposed in the light source grooves and respectively surrounded by the reflective surfaces. The light guide plates are respectively disposed in the light source grooves and respectively located between the reflective surfaces and the light-emitting elements. The first position limiting parts are respectively adapted to block the light guide plates from being separated from the reflective plate from the light outlets.

Abstract: A method for processing an integrated circuit includes forming a plurality of transistors. The method utilizes a reversed tone patterning process to selectively drive dipoles into the gate dielectric layers of some of the transistors while preventing dipoles from entering the gate dielectric layers of other transistors. This process can be repeated to produce a plurality of transistors each having different threshold voltages.

Abstract: A semiconductor device includes a channel portion disposed on and spaced apart from a substrate, a gate dielectric which includes an upper dielectric region disposed on the channel portion, a first inner gate structure disposed between the substrate and the upper dielectric region, and an outer gate structure including an outer work-function portion and a cap portion. The outer work-function portion covers the upper dielectric region and the first inner gate structure. The cap portion covers the outer work-function portion in a way that the cap portion is separated from the first inner gate structure. The first inner gate structure includes a first work-function material and a conductive material that is different from the first work-function material. The outer work-function portion includes a second work-function material that is different from the conductive material.

Abstract: According to an embodiment of the invention, a backlight driver of driving a light-emitting diode (LED) string via a driving transistor in a load path is provided. The LED string, the driving transistor, and an electrical load are coupled to form the load path. The backlight driver includes a current regulator and a headroom detection circuit. The current regulator is coupled to the driving transistor and the first terminal of the electrical load to control a driving current flowing through the load path according to at least a feedback voltage from a first terminal of the electrical load. The headroom detection circuit is coupled to the first terminal of the electrical load and a voltage regulator to control the voltage regulator to regulate a supply voltage to a first terminal of the LED string according to at least the feedback voltage.

Abstract: A processing device for processing opposing edges of a flexible sheet body is provided, including: a base; a first suction mechanism, arranged on the base and extending along a first direction, including first suction openings; at least one second suction mechanism, arranged on the base and extending in parallel with the first suction mechanism, including second suction openings, the at least one second suction mechanism and the first suction mechanism being relatively movable; a support platform, being adjustable and located between the first suction mechanism and the at least one second suction mechanism; at least one rail mechanism, arranged on the base; at least one gantry mechanism, movably arranged on the at least one rail mechanism; and at least two cutting mechanisms, arranged on the at least one gantry mechanism, at least one of the at least two cutting mechanisms being movable in a second direction.

Abstract: A method for manufacturing a semiconductor structure includes forming a semiconductor portion which has an exposed region; forming two fin sidewalls which are disposed at two opposite sides of the exposed region of the semiconductor portion, and which include a dielectric material; and performing an etching process such that the exposed region of the semiconductor portion is etched away to form a recess while a protection layer is formed to protect each of the fin sidewalls during the etching process. Other methods for manufacturing the semiconductor structure are also disclosed.

Abstract: A connector lock structure includes an insulating body, a plurality of terminals, a shell, a locking assembly, a sliding board, a pressing element and an unlocking tool. The insulating body is molded around the plurality of the terminals. The shell surrounds the insulating body. The locking assembly includes at least one lacking groove, and at least one elastic arm formed in the at least one lacking groove. The at least one elastic arm has a hook structure. The hook structure is cooperated with a blocking groove of a docking connector. The pressing element is mounted in the insulating body. The sliding board is slidably mounted under the pressing element. One end of the pressing element has a locking portion. The locking portion has a keyhole. The unlocking tool is inserted in the keyhole.