Patents by Inventor Chun-Fu Liao

Chun-Fu Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240153154
    Abstract: A coordinate generation system, a coordinate generation method, a computer readable recording medium with stored program, and a non-transitory computer program product are provided. The coordinate generation system includes processing units and a neural network module. The processing units are configured to obtain four vertex coordinates of an image. The vertex coordinates include first components and second components. The processing unit is configured to perform the following steps: obtaining first vector based on the first components of the four vertex coordinates and repeatedly concatenating the first vector so as to obtain a first input; obtaining second vector based on the second components of the four vertex coordinates and repeatedly concatenating the second vector so as to obtain a second input; and obtaining first output coordinate components and second output coordinate components of output coordinates based on the first input, the second input, and parameters of the neural network module.
    Type: Application
    Filed: January 17, 2023
    Publication date: May 9, 2024
    Applicant: REALTEK SEMICONDUCTOR CORP.
    Inventors: Yu-Hsuan Hung, Chun-Fu Liao, Kai-Ting Shr
  • Publication number: 20120183088
    Abstract: A lattice reduction architecture, a lattice reduction method and a detection system thereof are proposed. The proposed architecture performs lattice reduction on channel matrices corresponding to sub-carriers and includes G processing group blocks, which receives channel matrices corresponding to the sub-carriers, and each of the first to the G-1th processing group blocks includes k processing modules respectively processing k sub-carriers, and the Gth processing group block includes j processing modules, where j<=k. In each one of the processing group blocks, at least one processing module receives an initial matrix, where the processing module includes a lattice reduction processing unit provides a reduction matrix to at least one neighboring processing module when a lattice reduction algorithm is processed on a channel matrix corresponding to its respective sub-carrier for at least iteration loops according to the channel matrix and the received initial matrix.
    Type: Application
    Filed: January 14, 2011
    Publication date: July 19, 2012
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chun-Fu Liao, Fang-Chun Lan, Po-Lin Chiu, Yuan-Hao Huang