Abstract: A method for forming a semiconductor device structure includes forming nanostructures in a first region and a second region over a substrate. The method also includes forming a gate dielectric layer surrounding the nanostructures. The method also includes forming dummy structures between the nanostructures. The method also includes forming a dielectric layer over the nanostructures. The method also includes forming a dielectric structure between the nanostructures in the first region and nanostructures in the second region. The method also includes removing the dummy structures in the first region. The method also includes depositing a first work function layer over the nanostructures. The method also includes removing the first work function layer and the dummy structures in the second region. The method also includes depositing a second work function layer over the nanostructures.

Abstract: A method for processing an integrated circuit includes forming a plurality of transistors. The method utilizes a reversed tone patterning process to selectively drive dipoles into the gate dielectric layers of some of the transistors while preventing dipoles from entering the gate dielectric layers of other transistors. This process can be repeated to produce a plurality of transistors each having different threshold voltages.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first dielectric feature extending along a first direction, the first dielectric feature comprising a first dielectric layer having a first sidewall and a second sidewall opposing the first sidewall, a first semiconductor layer disposed adjacent the first sidewall, the first semiconductor layer extending along a second direction perpendicular to the first direction, a second dielectric feature extending along the first direction, the second dielectric feature disposed adjacent the first semiconductor layer, and a first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, and a portion of the first gate electrode layer is exposed to a first air gap.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a plurality of first nanostructures formed over a substrate, and a dielectric wall adjacent to the first nanostructures. The semiconductor structure also includes a first liner layer between the first nanostructures and the dielectric wall, and the first liner layer is in direct contact with the dielectric wall. The semiconductor structure also includes a gate structure surrounding the first nanostructures, and the first liner layer is in direct contact with a portion of the gate structure.

Abstract: A method for forming a semiconductor device is provided. The method includes forming a plurality of first channel nanostructures and a plurality of second channel nanostructures in an n-type device region and a p-type device region of a substrate, respectively, and sequentially depositing a gate dielectric layer, an n-type work function metal layer, and a cap layer surrounding each of the first and second channel nanostructures. The cap layer merges in first spaces between adjacent first channel nanostructures and merges in second spaces between adjacent second channel nanostructures. The method further includes selectively removing the cap layer and the n-type work function metal layer in the p-type device region, and depositing a p-type work function metal layer over the cap layer in the n-type device region and the gate dielectric layer in the p-type device region. The p-type work function metal layer merges in the second spaces.

Abstract: The present disclosure describes a semiconductor device having an isolation structure. The semiconductor structure includes a set of nanostructures on a substrate, a gate dielectric layer wrapped around the set of nanostructures, a work function metal layer on the gate dielectric layer and around the set of nanostructures, and the isolation structure adjacent to the set of nanostructures and in contact with the work function metal layer. A portion of the work function metal layer is on a top surface of the isolation structure.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first dielectric feature extending along a first direction, the first dielectric feature comprising a first dielectric layer having a first sidewall and a second sidewall opposing the first sidewall, a first semiconductor layer disposed adjacent the first sidewall, the first semiconductor layer extending along a second direction perpendicular to the first direction, a second dielectric feature extending along the first direction, the second dielectric feature disposed adjacent the first semiconductor layer, and a first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, and a portion of the first gate electrode layer is exposed to a first air gap.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The method includes the following steps. A fin structure extending along a first direction and having a lower fin structure and an upper fin structure disposed over the lower fin structure is formed, the upper fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. A sacrificial gate structure extending along a second direction perpendicular to the first direction is formed over the upper fin structure. Gate spacers are formed on the sacrificial gate structure. A portion of the sacrificial gate structure is removed to expose the gate spacers. Portions of the exposed gate spacers are removed to form a first gate trench with a first dimension along the first direction. The rest of the sacrificial gate structure is removed to form a second gate trench with a second dimension along the first direction under the first gate trench, wherein the first dimension is greater than the second dimension.

Abstract: A method for processing an integrated circuit includes forming a plurality of transistors. The method utilizes a reversed tone patterning process to selectively drive dipoles into the gate dielectric layers of some of the transistors while preventing dipoles from entering the gate dielectric layers of other transistors. This process can be repeated to produce a plurality of transistors each having different threshold voltages.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a substrate, and a gate structure formed over the fin structure. The gate structure includes a gate dielectric layer, a first conductive layer over the first conductive layer. The gate structure includes a fill layer over the first conductive layer. The semiconductor device structure includes a protection layer formed over the fill layer, and a top surface of the gate dielectric layer is lower than a top surface of the protection layer and higher than a top surface of the first conductive layer.

Abstract: A method of forming a semiconductor device includes forming a first dielectric layer over a first channel region in a first region and over a second channel region in a second region; introducing a first dipole element into the first dielectric layer in the first region to form a first dipole-containing gate dielectric layer in the first region; forming a second dielectric layer over the first dipole-containing gate dielectric layer; introducing fluorine into the second dielectric layer to form a first fluorine-containing gate dielectric layer over the first dipole-containing gate dielectric layer; and forming a gate electrode over the first fluorine-containing gate dielectric layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a substrate, and a gate structure formed over the fin structure. The gate structure includes a first layer, and a fill layer over the first layer. The gate structure includes a protection layer formed over the fill layer of the gate structure, and the protection layer is separated from the first layer by the fill layer.

Abstract: A semiconductor device is provided. The semiconductor device includes first channel nanostructures in a first device region, second channel nanostructures in a second device region, a dielectric fin at a boundary between the first device region and the second device region, a high-k dielectric layer surrounding each of the first channel nanostructures and each of the second channel nanostructures and over the dielectric fin, a first work function layer surrounding each of the first channel nanostructures and over the high-k dielectric layer and a second work function layer surrounding each of the second channel nanostructures and over the high-k dielectric layer and the first work function layer. The first work functional layer fully fills spaces between the first channel nanostructures and has an edge located above the dielectric fin. The second work functional layer fully fills spaces between the second channel nanostructures.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first dielectric feature extending along a first direction, the first dielectric feature comprising a first dielectric layer having a first sidewall and a second sidewall opposing the first sidewall, a first semiconductor layer disposed adjacent the first sidewall, the first semiconductor layer extending along a second direction perpendicular to the first direction, a second dielectric feature extending along the first direction, the second dielectric feature disposed adjacent the first semiconductor layer, and a first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, and a portion of the first gate electrode layer is exposed to a first air gap.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a substrate, and a gate structure formed over the fin structure. The gate structure includes a first layer, and a fill layer over the first layer. The gate structure includes a protection layer formed over the fill layer of the gate structure, and the protection layer is separated from the first layer by the fill layer.

Abstract: An electrical deposition apparatus includes a brush plating head. The brush plating head includes a plurality of channels, and there are openings at the same surface of the brush plating head. Each of the channels extends from within the brush plating head to each of the openings.

Abstract: The system for detecting volatile organic compounds (VOCs) of this present invention comprises a detecting material made by blending a nano-material and a conductive polymer. The system for detecting VOCs presents the property of high sensitivity, high sensing accuracy, quick response, and real-time VOC detecting, and is demonstrated in the present work for commercialization usage. The system for detecting VOCs can be easily operated to detect VOC without electronic detecting method, and hence this invention can reduce a lot of operation energy and procedure. Furthermore, when adding inorganic nanoparticles, the area of VOC exposure of this invention is increased and the molecular morphology variation of the detecting material is enhanced, and hence the detecting activity of the system for detecting VOCs is improved.

Abstract: A method of manufacturing a nozzle plate of a spray apparatus is provided. The method includes providing a conductive layer; forming a plurality of insulating layers on the conductive layer, wherein each of the insulating layers has at least one first tapered geometrical structure with mirror symmetry and a centroid with positional deviation from a first pattern center, and wherein the centroid of the first tapered geometrical structure is a barycenter of the first tapered geometrical structure; forming an electroplating layer on the conductive layer and part of the insulating layer, leaving the central part of the insulating layer exposed; and removing the conductive layer and the insulating layer to form a main body resulting in a plurality of orifices each having an inlet end and an outlet end on the electroplating layer.

Abstract: The system for detecting volatile organic compounds (VOCs) of this present invention comprises a detecting material made by blending a nano-material and a conductive polymer. The system for detecting VOCs presents the property of high sensitivity, high sensing accuracy, quick response, and real-time VOC detecting, and is demonstrated in the present work for commercialization usage. The system for detecting VOCs can be easily operated to detect VOC without electronic detecting method, and hence this invention can reduce a lot of operation energy and procedure. Furthermore, when adding inorganic nanoparticles, the area of VOC exposure of this invention is increased and the molecular morphology variation of the detecting material is enhanced, and hence the detecting activity of the system for detecting VOCs is improved.

Abstract: A display apparatus having a backlight module, a modulatable parallax barrier module, a polarizer film and a display panel is provided. The backlight module provides a linear polarized light having a first polarization direction. The modulatable parallax barrier module has an alignment state and a transparent state, and has a first alignment film with a first alignment direction on the light-emitting side. The linear polarized light passing through the modulatable parallax barrier module in the transparent state is kept in the first polarization direction, and passing through the modulatable parallax barrier module in the alignment state is transformed to a second polarization direction. The polarizer film has a transmission axis inclined toward either the first polarization direction or the second polarization direction. The modulatable parallax barrier module selects one of the alignment state and the transparent state according to an image information provided by the display panel.