Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.

Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.

Abstract: In a switch mode power supply of a video apparatus, a capacitor develops a supply voltage that is coupled to a main current conducting electrode of a driver transistor. The driver transistor drives a switching power transistor. An arrangement charges the charging capacitor when the video apparatus operates in standby mode. A delay circuit introduces a delay time between a time when the capacitor begins to be charged and the time when a switching control signal is applied to the driver transistor for operation in a run mode. Consequently, the capacitor develops sufficient voltage that insures sufficient base current to turn on the power transistor in to saturation prior to the time the switching control signal is applied to the driver transistor. Thus, a possible damage to the power transistor is prevented.

Abstract: In a television receiver, a microprocessor controls a horizontal deflection circuit which is coupled to run mode power supply to define a standby operating mode and a run operating mode. The microprocessor has a power-up reset input terminal which initializes operation upon application of AC mains power. The run mode power supply is coupled to at least one load which is subject to overcurrent or overvoltage faults. A fault detection circuit detects fault conditions in the run mode power supply loads such as overvoltage or overcurrent and anomalous vertical deflection current. Upon fault detection the fault detection circuit triggers a power up reset circuit which applies a momentary reset pulse to the power-up reset input of the microprocessor. Upon receipt of the reset pulse, the microprocessor controls the horizontal deflection circuit to place the run mode power supply in the standby operating mode.

Abstract: A television receiver is subject to certain operational conditions which result in poor, unreliable or unusable separated sync pulse signals. During such conditions the use of unsuitable sync signals for synchronization and the like is inhibited to prevent mis-triggering or spurious synchronization. A television receiver contains circuitry for extracting a sync signal, a voltage controlled oscillator (VCO) for generating a scanning signal, and a comparator comparing the scanning signal to the separated sync signal. A microprocessor is used to verify the separate sync signal for invalid or unusable signals and has an output activated during such conditions. The phase comparator has a current output coupled to a integrating capacitor or LPF which develops a varying positive or negative voltage to raise or lower the frequency of the VCO for scanning in phase with the separated sync.

Abstract: A television receiver has a switched mode power supply for regulating an output voltage, including a power transformer having a primary winding coupled to an unregulated voltage via a power transistor. The power transistor is controlled by pulses from the output of a controller. In order to sweep the base-emitter charge from the power transistor in order to end collector-emitter conduction, the base of the power transistor is coupled to the output of the pulse generating controller via a capacitor in parallel with at least one diode. During a pulse from the controller, the capacitor is charged to a voltage equal to the forward biased drop across the diode(s). At the end of a pulse at the output of the controller, the voltage across the capacitor provides a negative voltage at the base of the transistor, thus sweeping out the base-emitter charge and sharply turning the transistor off.

Abstract: A television receiver has a switched mode power supply for regulating output voltages including the B+ output to a flyback transformer, by generation of output pulses to a power transformer. A controller for the power supply is coupled in two feedback loops, one responsive to a pulse width modulator coupled to the flyback transformer and the other comparing the output voltage with an internal reference for free running operation. The first feedback loop takes precedence and is active in the run mode of the television receiver. In the standby mode when horizontal rate pulses are absent, the second feedback loop takes over. The second feedback loop has a different reference level than the first, such that when switching from the run mode to the standby mode a transition interval occurs in which no pulses are output by the controller, thereby causing the B+ voltage to the flyback transformer to fall.

Abstract: A vertical deflection ramp voltage is generated by the charge and discharge of a resistor capacitor combination. The voltage ramp is coupled to an amplifier which drives a current through a deflection coil producing a magnetic deflection field. The ramp voltage produced by the resistor capacitor combination has an inherent exponential shape which is linearized to prevent vertical linearity errors in the deflected electron beam. Linearization is achieved by multiple feedback paths which couple the amplifier output voltage and a voltage sample of the deflection coil current to the ramp forming resistor. These feedback signals are of a polarity such to establish a constant voltage across the resistor which consequently produces a constant current flow through the resistor. Hence with constant current flow in the resistor, a linear voltage ramp is produced across the capacitor and exponential deflection cramping is avoided.