Patents by Inventor Chun-Han TSAO

Chun-Han TSAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160204154
    Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug.
    Type: Application
    Filed: March 21, 2016
    Publication date: July 14, 2016
    Inventors: Shih Pei Chou, Hung-Wen Hsu, Ching-Chung Su, Chun-Han Tsao, Chia-Chieh Lin, Shu-Ting Tsai, Jiech-Fun Lu, Shih-Chang Liu, Yeur-Luen Tu, Chia-Shiung Tsai
  • Patent number: 9293392
    Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: March 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih Pei Chou, Hung-Wen Hsu, Ching-Chung Su, Chun-Han Tsao, Lin Chia-Chieh, Shu-Ting Tsai, Jiech-Fun Lu, Shih-Chang Liu, Yeur-Luen Tu, Chia-Shiung Tsai
  • Patent number: 9252296
    Abstract: A semiconductor device includes a substrate having a first side and a second side opposite the first side. The substrate has a sensor region proximate the first side. The semiconductor device also includes a first compressive layer over the second side of the substrate. The semiconductor device further includes a light blocking element over the first compressive layer. The semiconductor device additionally includes a second compressive layer over the first compressive layer and covering a portion of the light blocking element. The semiconductor device also includes a third compressive layer between the second compressive layer and the portion of the light blocking element.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: February 2, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Han Tsao, Chih-Yu Lai, Chih-Hui Huang, Cheng-Ta Wu, Yeur-Luen Tu, Ching-Chun Wang, Shyh-Fann Ting, Chia-Shiung Tsai
  • Publication number: 20150263055
    Abstract: A semiconductor device includes a substrate having a first side and a second side opposite the first side. The substrate has a sensor region proximate the first side. The semiconductor device also includes a first compressive layer over the second side of the substrate. The semiconductor device further includes a light blocking element over the first compressive layer. The semiconductor device additionally includes a second compressive layer over the first compressive layer and covering a portion of the light blocking element. The semiconductor device also includes a third compressive layer between the second compressive layer and the portion of the light blocking element.
    Type: Application
    Filed: May 15, 2015
    Publication date: September 17, 2015
    Inventors: Chun-Han TSAO, Chih-Yu LAI, Chih-Hui HUANG, Cheng-Ta WU, Yeur-Luen TU, Ching-Chun WANG, Shyh-Fann TING, Chia-Shiung TSAI
  • Publication number: 20150214082
    Abstract: An apparatus for and a method of bonding a first substrate and a second substrate are provided. In an embodiment a first wafer chuck has a first curved surface and a second wafer chuck has a second curved surface. A first wafer is placed on the first wafer chuck and a second wafer is placed on a second wafer chuck, such that both the first wafer and the second wafer are pre-warped prior to bonding. Once the first wafer and the second wafer have been pre-warped, the first wafer and the second wafer are bonded together.
    Type: Application
    Filed: January 24, 2014
    Publication date: July 30, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Hui Huang, Chun-Han Tsao, Sheng-Chau Chen, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 9059057
    Abstract: An image sensor device including a semiconductor substrate that includes an array region and a black level correction region. The array region contains a plurality of radiation-sensitive pixels. The black level correction region contains one or more reference pixels. The substrate has a front side and a back side. The image sensor device includes a first compressively-stressed layer formed on the back side of the substrate. The first compressively-stressed layer contains silicon oxide, and is negatively charged. The second compressively-stressed layer contains silicon nitride, and is negatively charged. A metal shield is formed over at least a portion of the black level correction region. The image sensor device includes a third compressively-stressed layer formed on the metal shield and the second compressively-stressed layer. The third compressively-stressed layer contains silicon oxide. A sidewall of the metal shield is protected by the third compressively-stressed layer.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: June 16, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Han Tsao, Chih-Yu Lai, Chih-Hui Huang, Cheng-Ta Wu, Yeur-Luen Tu, Ching-Chun Wang, Shyh-Fann Ting, Chia-Shiung Tsai
  • Publication number: 20150069619
    Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug.
    Type: Application
    Filed: September 6, 2013
    Publication date: March 12, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih Pei Chou, Hung-Wen Hsu, Ching-Chung Su, Chun-Han Tsao, Lin Chia-Chieh, Shu-Ting Tsai, Jiech-Fun Lu, Shih-Chang Liu, Yeur-Luen Tu, Chia-Shiung Tsai
  • Publication number: 20130329102
    Abstract: An image sensor device including a semiconductor substrate that includes an array region and a black level correction region. The array region contains a plurality of radiation-sensitive pixels. The black level correction region contains one or more reference pixels. The substrate has a front side and a back side. The image sensor device includes a first compressively-stressed layer formed on the back side of the substrate. The first compressively-stressed layer contains silicon oxide, and is negatively charged. The second compressively-stressed layer contains silicon nitride, and is negatively charged. A metal shield is formed over at least a portion of the black level correction region. The image sensor device includes a third compressively-stressed layer formed on the metal shield and the second compressively-stressed layer. The third compressively-stressed layer contains silicon oxide. A sidewall of the metal shield is protected by the third compressively-stressed layer.
    Type: Application
    Filed: June 8, 2012
    Publication date: December 12, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Han TSAO, Chih-Yu LAI, Chih-Hui HUANG, Cheng-Ta WU, Yeur-Luen TU, Ching-Chun WANG, Shyh-Fann TING, Chia-Shiung TSAI