Abstract: A matrix multiplier includes an operation circuit and a controller. The operation circuit is coupled to the controller. The controller is configured to control the operation circuit to reuse a left fractal matrix Asr in n consecutive clock cycles, and control the operation circuit to use a right fractal matrix Brt in n right fractal matrices in each of the n consecutive clock cycles. The operation circuit is configured to multiply, in each of the n consecutive clock cycles, the left fractal matrix by the right fractal matrix in the n right fractal matrices to obtain n matrix operation results.

Abstract: A splitting circuit included in a floating-point number calculation circuit splits a mantissa part of a first floating-point number and a mantissa part of a second floating-point number. An exponential processing circuit obtains a second number of shifted bits of each mantissa part obtained after splitting. A calculation circuit calculates a product of the mantissa part of the first floating-point number and the mantissa part of the second floating-point number based on each mantissa part obtained after splitting and the second number of shifted bits of each mantissa part obtained after splitting. The floating-point number calculation circuit can split a large bit-width floating-point number into small bit-width floating-point numbers, so that a small bit-width multiplier is used to calculate the large bit-width floating-point number.

Abstract: A neural network accelerator is provided, including: a preprocessing module (301), configured to perform first forward winograd transform on a target matrix corresponding to an input feature map, to obtain a transformed target matrix, where the preprocessing module (301) is further configured to perform second forward winograd transform on a convolution kernel, to obtain a transformed convolution kernel; a matrix operation module (302), configured to perform a matrix multiplication operation on a first matrix and a second matrix, to obtain a multiplication result, where the first matrix is constructed based on the transformed target matrix, and the second matrix is constructed based on the transformed convolution kernel; and a vector operation module (303), configured to perform inverse winograd transform on the multiplication result, to obtain an output feature map.

Abstract: A multiplier (500) configured to simultaneously implement a plurality of low bit width multiplication operations is provided. The multiplier (500) includes a multiplicator input end (550) for receiving two low bit width multiplicators, a multiplicand input end (560) for receiving two low bit width multiplicands, a mask circuit (540) for masking each low bit width multiplicator, and a multiplication operation circuit (502) for multiplying a mask result and a multiplicand. When a sum of bit widths of the multiplicators is smaller than the multiplicator input end (550) and a sum of bit widths of the multiplicands is smaller than the multiplicand input end (560), masking is performed on each of the low bit width multiplicators, so that the multiplier (500) may respectively implement two low bit width multiplication operations, which resolves a waste of hardware resources that occurs because the multiplier can only process multiplication operations in one data format.

Abstract: The invention relates to an apparatus for selecting candidates in a K-Best algorithm of a MIMO decoder. The K-Best algorithm uses a layered structure comprising a first layer and subsequent layers. In each subsequent layer 2L candidates are selected by iteratively carrying out a selection step, wherein in the selection step the apparatus is configured to calculate and select at least two candidates having minimum distance values of a candidate group, and after each iteratively carried out selection step, the selected at least two candidates are sent to a further subsequent layer for iteratively generating a further candidate group of 2L candidates in the further subsequent layer.

Abstract: The invention relates to an apparatus for selecting candidates in a K-Best algorithm of a MIMO decoder. The K-Best algorithm uses a layered structure comprising a first layer and subsequent layers. In each subsequent layer 2L candidates are selected by iteratively carrying out a selection step, wherein in the selection step the apparatus is configured to calculate and select at least two candidates having minimum distance values of a candidate group, and after each iteratively carried out selection step, the selected at least two candidates are sent to a further subsequent layer for iteratively generating a further candidate group of 2L candidates in the further subsequent layer.

Abstract: A computer processor implementable method of decoding low-density parity-check (LDPC) code, comprising: receiving a log-likelihood-ratio (LLR) input bitstream; performing a combined bit-deinterleaving and reordering process on the LLR input bitstream and storing in a physical memory space, comprising: determining a logical memory address for each LLR bit in the LLR input bitstream, determining a physical memory address for each LLR bit in the LLR input bitstream from logical memory address of the LLR bit; decoding the LLR input bitstream stored in the physical memory space; and performing a combined de-reordering and de-mapping process on the decoded LLR input bitstream.

Abstract: A computer processor implementable method of decoding low-density parity-check (LDPC) code, comprising: receiving a log-likelihood-ratio (LLR) input bitstream; performing a combined bit-deinterleaving and reordering process on the LLR input bitstream and storing in a physical memory space, comprising: determining a logical memory address for each LLR bit in the LLR input bitstream, determining a physical memory address for each LLR bit in the LLR input bitstream from logical memory address of the LLR bit; decoding the LLR input bitstream stored in the physical memory space; and performing a combined de-reordering and de-mapping process on the decoded LLR input bitstream.

Abstract: A computer processor implementable method of decoding low-density parity-check (LDPC) code, comprising: receiving a log-likelihood-ratio (LLR) input bitstream; performing a combined bit-deinterleaving and reordering process on the LLR input bitstream and storing in a physical memory space, comprising: determining a logical memory address for each LLR bit in the LLR input bitstream, determining a physical memory address for each LLR bit in the LLR input bitstream from logical memory address of the LLR bit; decoding the LLR input bitstream stored in the physical memory space; and performing a combined de-reordering and de-mapping process on the decoded LLR input bitstream.

Abstract: A computer processor implementable method of decoding low-density parity-check (LDPC) code, comprising: receiving a log-likelihood-ratio (LLR) input bitstream; performing a combined bit-deinterleaving and reordering process on the LLR input bitstream and storing in a physical memory space, comprising: determining a logical memory address for each LLR bit in the LLR input bitstream, determining a physical memory address for each LLR bit in the LLR input bitstream from logical memory address of the LLR bit; decoding the LLR input bitstream stored in the physical memory space; and performing a combined de-reordering and de-mapping process on the decoded LLR input bitstream.