Abstract: A method of fabricating an ESD protection circuit without salicide formation is described. First, isolation regions and gate structures are formed on a semiconductor substrate, then device regions and ESD circuit regions are then defined. Next, a first dielectric layer is deposited the over entire semiconductor substrate, and heavily doped source/drain regions are formed in ESD protection circuit region. Next, a second dielectric layer and the first dielectric layer of NMOS areas are etched to form spacers on the sidewalls of the gate structures. Then, N.sup.+ /P.sup.+ ion implantation are performed to form heavily doped source/drain regions of NMOS and PMOS, respectively. Finally, salicide process is performed to form silicide over the exposed surface of the gate, source/drain regions in the NMOS and PMOS active device regions.