Patents by Inventor Chun-Hao Chou

Chun-Hao Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240405053
    Abstract: Some implementations described herein include a complementary metal oxide semiconductor image sensor device and techniques to form the complementary metal oxide semiconductor image sensor device. The complementary metal oxide semiconductor image sensor device includes a includes a first array of photodiodes stacked over a second array of photodiodes. A polarization structure is between the first array of photodiodes and the second array of photodiodes. Signaling generated by the first array of photodiodes (e.g., signaling corresponding to unpolarized light waves) may be multiplexed with signaling generated by the second array of photodiodes (e.g., signaling corresponding to polarized light waves). The complementary metal oxide semiconductor image sensor device further includes a filter structure that filters visible light waves and near infrared light waves amongst the first array of photodiodes and the second array of photodiodes.
    Type: Application
    Filed: May 31, 2023
    Publication date: December 5, 2024
    Inventors: Chun-Liang LU, Wei-Lin CHEN, Chun-Hao CHOU, Kuo-Cheng LEE
  • Publication number: 20240395785
    Abstract: A method and wafer stack that includes a first wafer component, a second wafer component, and third wafer component. The first wafer component includes a frontside and a backside. The wafer stack also includes a second wafer component having a frontside and a backside, such that the frontside of the second wafer component is bonded to the frontside of the first wafer component. In addition, the wafer stack includes a third wafer component having a frontside and a backside, such that the frontside of the third wafer component is bonded to the backside of the second wafer component. The first wafer component includes a composite metal grid array with one or more photodiodes formed on the backside.
    Type: Application
    Filed: May 23, 2023
    Publication date: November 28, 2024
    Inventors: Ming-Hsien Yang, Chun-Hao Chou, Chia-Yu Wei, Kuo-Cheng Lee, Chung-Liang Cheng, Sheng-Chau Chen
  • Patent number: 12154924
    Abstract: Various embodiments of the present application are directed to a narrow band filter with high transmission and an image sensor comprising the narrow band filter. In some embodiments, the filter comprises a first distributed Bragg reflector (DBR), a second DBR, a defect layer between the first and second DBRs, and a plurality of columnar structures. The columnar structures extend through the defect layer and have a refractive index different than a refractive index of the defect layer. The first and second DBRs define a low transmission band, and the defect layer defines a high transmission band dividing the low transmission band. The columnar structures shift the high transmission band towards lower or higher wavelengths depending upon a refractive index of the columnar structures and a fill factor of the columnar structures.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: November 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng Yu Huang, Chun-Hao Chuang, Chien-Hsien Tseng, Kazuaki Hashimoto, Keng-Yu Chou, Wei-Chieh Chiang, Wen-Hau Wu
  • Publication number: 20240387574
    Abstract: Implementations described herein reduce electron-hole pair generation due to silicon dangling bonds in pixel sensors. In some implementations, the silicon dangling bonds in a pixel sensor may be passivated by silicon-fluorine (Si—F) bonding in various portions of the pixel sensor such as a transfer gate contact via or a shallow trench isolation region, among other examples. The silicon-fluorine bonds are formed by fluorine implantation and/or another type of semiconductor processing operation. In some implementations, the silicon-fluorine bonds are formed as part of a cleaning operation using fluorine (F) such that the fluorine may bond with the silicon of the pixel sensor. Additionally, or alternatively, the silicon-fluorine bonds are formed as part of a doping operation in which boron (B) and/or another p-type doping element is used with fluorine such that the fluorine may bond with the silicon of the pixel sensor.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Wei-Lin CHEN, Chun-Hao CHOU, Kuo-Cheng LEE
  • Publication number: 20240387599
    Abstract: An array of nanoscale structures over photodiodes of a pixel array improves quantum efficiency (QE) for shorter wavelengths of light, such as green light and blue light. The nanoscale structures may be used without high absorption (HA) structures (e.g., when the pixel array is configured only for visible light) or may at least partially surround HA structures (e.g., when the pixel array is configured both for visible light and near infrared light). Additionally, the array of nanoscale structures may be formed using photolithography such that the nanoscale structures are approximately spaced at regular intervals. Therefore, QE for the pixel array is improved more than if the array of nanoscale structures were to be formed using a random (or quasi-random) process.
    Type: Application
    Filed: May 17, 2023
    Publication date: November 21, 2024
    Inventors: Wei-Lin CHEN, Chun-Hao CHOU, Kun-Hui LIN, Kuo-Cheng LEE
  • Patent number: 12148783
    Abstract: Various embodiments of the present disclosure are directed towards an image sensor device including a first image sensor element and a second image sensor element disposed within a substrate. An interconnect structure is disposed along a front-side surface of the substrate and comprises a plurality of conductive wires, a plurality of conductive vias, and a first absorption structure. The first image sensor element is configured to generate electrical signals from electromagnetic radiation within a first range of wavelengths. The second image sensor element is configured to generate electrical signals from the electromagnetic radiation within a second range of wavelengths that is different than the first range of wavelengths. The second image sensor element is laterally adjacent to the first image sensor element. Further, the first image sensor element overlies the first absorption structure and is spaced laterally between opposing sidewalls of the first absorption structure.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: November 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Keng-Yu Chou, Cheng Yu Huang, Chun-Hao Chuang, Wen-Hau Wu, Wei-Chieh Chiang, Wen-Chien Yu, Chih-Kung Chang
  • Publication number: 20240379714
    Abstract: Some embodiments relate to a CMOS image sensor disposed on a substrate. A plurality of pixel regions comprising a plurality of photodiodes, respectively, are configured to receive radiation that enters a back-side of the substrate. A boundary deep trench isolation (BDTI) structure is disposed at boundary regions of the pixel regions, and includes a first set of BDTI segments extending in a first direction and a second set of BDTI segments extending in a second direction perpendicular to the first direction to laterally surround the photodiode. The BDTI structure comprises a first material. A pixel deep trench isolation (PDTI) structure is disposed within the BDTI structure and overlies the photodiode. The PDTI structure comprises a second material that differs from the first material, and includes a first PDTI segment extending in the first direction such that the first PDTI segment is surrounded by the BDTI structure.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Inventors: Cheng Yu Huang, Wei-Chieh Chiang, Keng-Yu Chou, Chun-Hao Chuang, Wen-Hau Wu, Chih-Kung Chang
  • Publication number: 20240379703
    Abstract: The present disclosure relates to an integrated chip including a substrate and a pixel. The pixel includes a photodetector. The photodetector is in the substrate. The integrated chip further includes a first inner trench isolation structure and an outer trench isolation structure that extend into the substrate. The first inner trench isolation structure laterally surrounds the photodetector in a first closed loop. The outer trench isolation structure laterally surrounds the first inner trench isolation structure along a boundary of the pixel in a second closed loop and is laterally separated from the first inner trench isolation structure. Further, the integrated chip includes a scattering structure that is defined, at least in part, by the first inner trench isolation structure and that is configured to increase an angle at which radiation impinges on the outer trench isolation structure.
    Type: Application
    Filed: July 21, 2024
    Publication date: November 14, 2024
    Inventors: Cheng Yu Huang, Chun-Hao Chuang, Keng-Yu Chou, Wei-Chieh Chiang, Wen-Hau Wu, Chih-Kung Chang
  • Publication number: 20240380986
    Abstract: An image sensor device has a first number of first pixels disposed in a substrate and a second number of second pixels disposed in the substrate. The first number is substantially equal to the second number. A light-blocking structure disposed over the first pixels and the second pixels. The light-blocking structure defines a plurality of first openings and second openings through which light can pass. The first openings are disposed over the first pixels. The second openings are disposed over the second pixels. The second openings are smaller than the first openings. A microcontroller is configured to turn on different ones of the second pixels at different points in time.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Inventors: Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee, Hsin-Chi Chen
  • Publication number: 20240379611
    Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first wafer including a first metal structure within a body of the first wafer. The semiconductor structure also includes a second wafer including a second metal structure within a body of the second wafer, where the first wafer is coupled to the second wafer at an interface. The semiconductor structure further includes a metal bonding structure coupled to the first metal structure and the second metal structure and extending through the interface.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: Chun-Liang LU, Wei-Lin CHEN, Chun-Hao CHOU, Kuo-Cheng LEE
  • Publication number: 20240371895
    Abstract: A method for forming an image sensor package is provided. An image sensor chip is formed over a package substrate. A protection layer is formed overlying the image sensor chip. The protection layer has a planar top surface and a bottom surface lining and contacting structures under the protection layer. An opening is formed into the protection layer and spaced around a periphery of the image sensor chip. A light shielding material is filled in the opening to form an on-wafer shield structure having a sidewall directly contact the protection layer.
    Type: Application
    Filed: July 17, 2024
    Publication date: November 7, 2024
    Inventors: Wen-Hau Wu, Chun-Hao Chuang, Kazuaki Hashimoto, Keng-Yu Chou, Wei-Chieh Chiang, Cheng Yu Huang
  • Publication number: 20240363668
    Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes at least one device on a front side of a semiconductor substrate. A plurality of grating layers are under the at least one device. The plurality of grating layers include at least a first material having a first refractive index alternating with a second material having a second refractive index. Contacts extend through an interlevel dielectric material, and further extend through the semiconductor substrate, to directly contact at least one of the first material and the second material below the at least one device and below the semiconductor substrate underlying the interlevel dielectric material.
    Type: Application
    Filed: July 11, 2024
    Publication date: October 31, 2024
    Inventors: Cheng Yu Huang, Chun-Hao Chuang, Chien-Hsien Tseng, Kazuaki Hashimoto, Keng-Yu Chou, Wei-Chieh Chiang, Wen-Hau Wu
  • Publication number: 20240355847
    Abstract: A CMOS image sensor includes a unit pixel array including a photodiode array, a color filter array, a micro-lens array, and a grid isolation structure laterally separating adjacent color filters. The grid isolation structure includes a first low-n grid, a second low-n grid underlying the first low-n grid, and a metal grid within the second low-n grid, the first low-n grid being narrower than the second low-n grid. The color filter array includes color filter matrixes, all color filter matrixes have the same arrangement pattern. Sizes of color filters in each color filter matrix vary depending on locations of the color filters in the color filter matrix. In an edge portion, a distance between a center of a color filter matrix and a center of a corresponding unit pixel matrix in plan view varies depending on a location of the unit pixel matrix in the CMOS image sensor.
    Type: Application
    Filed: April 20, 2023
    Publication date: October 24, 2024
    Inventors: Ming-Hsien YANG, Wei-Chih WENG, Chun-Wei CHIA, Chun-Hao CHOU, Tse Yu TU, Chien Nan TU, Chun-Liang LU, Kuo-Cheng LEE
  • Patent number: 12113086
    Abstract: Apparatus and methods for sensing long wavelength light are described herein. A semiconductor device includes: a carrier; a device layer on the carrier; a semiconductor layer on the device layer, and an insulation layer on the semiconductor layer. The semiconductor layer includes isolation regions and pixel regions. The isolation regions are or include a first semiconductor material. The pixel regions are or include a second semiconductor material that is different from the first semiconductor material.
    Type: Grant
    Filed: August 9, 2023
    Date of Patent: October 8, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee, Ying-Hao Chen
  • Patent number: 12113042
    Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first wafer including a first metal structure within a body of the first wafer. The semiconductor structure also includes a second wafer including a second metal structure within a body of the second wafer, where the first wafer is coupled to the second wafer at an interface. The semiconductor structure further includes a metal bonding structure coupled to the first metal structure and the second metal structure and extending through the interface.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: October 8, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Liang Lu, Wei-Lin Chen, Chun-Hao Chou, Kuo-Cheng Lee
  • Publication number: 20240324872
    Abstract: An optical system applied to an optical biometer is disclosed. The optical system includes a light source, first and second switchable reflectors, and first and second fixed reflectors. The first switchable reflector is disposed corresponding to the light source. The second switchable reflector is disposed corresponding to an eye. In a first mode, the first and second switchable reflectors are switched to a first state, and the incident light emitted by the light source is reflected by the first fixed reflector along a first optical path and then emitted to a first position of the eye. In a second mode, the first and second switchable reflectors are switched to a second state, and the incident light is sequentially reflected by the first switchable reflector, the second fixed reflector and the second switchable reflector along a second optical path and then emitted to a second position of the eye.
    Type: Application
    Filed: March 28, 2024
    Publication date: October 3, 2024
    Inventors: Meng-Shin YEN, Yen-Jen CHANG, Che-Liang TSAI, Chun-Nan LIN, Sung-Yang WEI, Hsuan-Hao CHAO, Chung-Ping CHUANG, William WANG, Tung-Yu LEE, Chung-Cheng CHOU
  • Publication number: 20240332115
    Abstract: The present disclosure describes heat dissipation structures formed in functional or non-functional areas of a three-dimensional chip structure. These heat dissipation structures are configured to route the heat generated within the three-dimensional chip structure to designated areas on or outside the three-dimensional chip structure. For example, the three-dimensional chip structure can include a plurality of chips vertically stacked on a substrate, a first passivation layer interposed between a first chip and a second chip of the plurality of chips, and a heat dissipation layer embedded in the first passivation layer and configured to allow conductive structures to pass through.
    Type: Application
    Filed: June 11, 2024
    Publication date: October 3, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun-Wei CHENG, Chun-Hao CHOU, Kuo-Cheng LEE, Ying-Hao CHEN
  • Patent number: 12100720
    Abstract: A method for forming an image sensor package is provided. An image sensor chip is formed over a package substrate. A protection layer is formed overlying the image sensor chip. The protection layer has a planar top surface and a bottom surface lining and contacting structures under the protection layer. An opening is formed into the protection layer and spaced around a periphery of the image sensor chip. A light shielding material is filled in the opening to form an on-wafer shield structure having a sidewall directly contact the protection layer.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: September 24, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Hau Wu, Chun-Hao Chuang, Kazuaki Hashimoto, Keng-Yu Chou, Wei-Chieh Chiang, Cheng Yu Huang
  • Publication number: 20240313118
    Abstract: The present disclosure provides a semiconductor device that includes a semiconductor fin disposed over a substrate, an isolation structure at least partially surrounding the fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, where an extended portion of the epitaxial S/D feature extends over the isolation structure, and a silicide layer disposed on the epitaxial S/D feature, where the silicide layer covers top, bottom, sidewall, front, and back surfaces of the extended portion of the S/D feature.
    Type: Application
    Filed: May 24, 2024
    Publication date: September 19, 2024
    Inventors: Pei-Hsun Wang, Chih-Chao Chou, Shih-Cheng Chen, Jung-Hung Chang, Jui-Chien Huang, Chun-Hsiung Lin, Chih-Hao Wang
  • Publication number: 20240304653
    Abstract: Some implementations described herein provide an optoelectronic device and methods of formation. The optoelectronic device is fabricated using a series of operations that includes a patterning operation using a layer of a negative photoresist material, followed by a single dry etch operation, a single wet strip operation, and a single wet etch operation. The series of operations may include a reduced number of operations relative to another series of operations that include a patterning operation using a layer of a positive photoresist material. Through the reduced number of operations, handling-induced damage to the device may be reduced. Additionally, the high absorption structure may include a quantum efficiency that is greater relative to another quantum efficiency of another high absorption structure formed through the series of operations that include the patterning operation using the layer of the positive photoresist material.
    Type: Application
    Filed: March 10, 2023
    Publication date: September 12, 2024
    Inventors: Chun-Liang LU, Chun-Hao CHOU, Kuo-Cheng LEE, Wei-Lin CHEN