Patents by Inventor Chun-Hao Chou

Chun-Hao Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250151372
    Abstract: A method includes forming first semiconductive sheets over a substrate and arranged in a vertical direction, and second semiconductive sheets over the substrate and arranged in the vertical direction, wherein a number of the second semiconductive sheets is different than a number of the first semiconductive sheets; forming first source/drain regions on either side of each of the first semiconductive sheets, and second source/drain regions on either side of each of the second semiconductive sheets; forming a first gate around each of the first semiconductive sheets, and a second gate around each of the second semiconductive sheets.
    Type: Application
    Filed: November 3, 2023
    Publication date: May 8, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun Yi CHOU, Guan-Lin CHEN, Shi Ning JU, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20250134468
    Abstract: A signal sensing device includes a signal amplifying structure to amplify the strength of the measured signal. The signal sensing device includes a body, a signal sensing element, and a signal amplifying portion. The signal sensing element is disposed in the body and includes a signal transmission section and a signal sensing section in electrical connection with the signal transmission section. The signal amplifying portion includes a plurality of protruding structures protruding outward from the body. Each of the plurality of protruding structures is cylindrical and has a diameter of 250-400 ?m and a height of 40-75 ?m. When a portion of the body forms a surrounding portion surrounding a to-be-sensed target, a portion or an entirety of the signal sensing section is located on the surrounding portion, and the signal amplifying portion is partially or entirely in contact with the to-be-sensed target.
    Type: Application
    Filed: October 31, 2023
    Publication date: May 1, 2025
    Inventors: Shu-Hung Huang, Chun-Chieh Tseng, Jui-Han Lu, Chun-Ming Chen, Ping-Ruey Chou, Yen-Hsin Kuo, Tung-Lin Tsai, Yen-Hao Chang, Sheng-Hua Wu, Chia-Hua Chang, Wen-Ming Cheng
  • Publication number: 20250141091
    Abstract: A signal sensing device includes a body and two signal sensing elements disposed in the body. An insulating layer is sandwiched between the two signal sensing elements. Each of the two signal sensing elements incudes a signal transmission section and a signal sensing section in electrical connection with the signal transmission section. The signal transmission sections are planar antennae parallel to each other and each having an antenna shape of meander-line type. The antenna shape of each transmission section has a vertical projection on a plane parallel to each signal transmission section. The vertical projections of the antenna shapes do not overlap completely. When a portion of the body forms a surrounding portion which surrounds a to-be-sensed target, a portion or an entirety of each signal sensing section is located on the surrounding portion.
    Type: Application
    Filed: October 31, 2023
    Publication date: May 1, 2025
    Inventors: Shu-Hung Huang, Chun-Chieh Tseng, Jui-Han Lu, Chun-Ming Chen, Ping-Ruey Chou, Yen-Hsin Kuo, Tung-Lin Tsai, Yen-Hao Chang, Sheng-Hua Wu, Chia-Hua Chang, Wen-Ming Cheng
  • Publication number: 20250126912
    Abstract: A semiconductor image-sensing structure includes a reflective grid and a reflective shield disposed over a substrate. The reflective grid is disposed in a first region, and the reflective shield is disposed in a second region separated from the first region. A thickness of the reflective shield is greater than a thickness of the reflective grid.
    Type: Application
    Filed: December 26, 2024
    Publication date: April 17, 2025
    Inventors: MING-HSIEN YANG, WEN-I HSU, KUAN-FU LU, FENG-CHI HUNG, JEN-CHENG LIU, DUN-NIAN YAUNG, CHUN-HAO CHOU, KUO-CHENG LEE
  • Patent number: 12278254
    Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes forming a first image sensor element within a first substrate and a second image sensor element within a second substrate. The first image sensor element is configured to generate electrical signals from electromagnetic radiation within a first range of wavelengths and the second image sensor element is configured to generate electrical signals from electromagnetic radiation within a second range of wavelengths. A plurality of deposition processes are performed to form a band-pass filter over the second substrate. The band-pass filter has a plurality of alternating layers of a first material having a first refractive index and a second material having a second refractive index that is less than the first refractive index. The first substrate is bonded to the band-pass filter.
    Type: Grant
    Filed: July 17, 2023
    Date of Patent: April 15, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng Yu Huang, Chun-Hao Chuang, Chien-Hsien Tseng, Kazuaki Hashimoto, Keng-Yu Chou, Wei-Chieh Chiang, Wen-Hau Wu
  • Patent number: 12278249
    Abstract: In some embodiments, an image sensor is provided. The image sensor includes a photodetector disposed in a semiconductor substrate. A wave guide filter having a substantially planar upper surface is disposed over the photodetector. The wave guide filter includes a light filter disposed in a light filter grid structure. The light filter includes a first material that is translucent and has a first refractive index. The light filter grid structure includes a second material that is translucent and has a second refractive index less than the first refractive index.
    Type: Grant
    Filed: November 21, 2023
    Date of Patent: April 15, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng Yu Huang, Chun-Hao Chuang, Chien-Hsien Tseng, Kazuaki Hashimoto, Keng-Yu Chou, Wei-Chieh Chiang, Wen-Chien Yu, Ting-Cheng Chang, Wen-Hau Wu, Chih-Kung Chang
  • Publication number: 20250118684
    Abstract: A semiconductor device includes a first wafer comprising a first portion of a seal ring structure within a body of the first wafer. The semiconductor device includes a second wafer comprising a second portion of the seal ring structure within a body of the second wafer. The second wafer is affixed to the first wafer such that the second portion of the seal ring structure is on the first portion of the seal ring structure. The semiconductor device includes a trench structure comprising a first trench in the first wafer and a second trench in the second wafer, where the first trench and the second trench are on a same side of the seal ring structure.
    Type: Application
    Filed: December 18, 2024
    Publication date: April 10, 2025
    Inventors: Chun-Liang LU, Chun-Wei CHIA, Chun-Hao CHOU, Kuo-Cheng LEE
  • Publication number: 20250120197
    Abstract: A pixel sensor array may include a plurality of pixel sensors configured to generate color information associated with incident light, and a time of flight (ToF) sensor circuit configured to generate distance information associated with the incident light. The color information and the distance information may be used to generate a three-dimensional (3D) ToF color image. The ToF sensor circuit may be included under a DTI structure surrounding the plurality of pixel sensors in a top view of the pixel sensor array.
    Type: Application
    Filed: October 5, 2023
    Publication date: April 10, 2025
    Inventors: Ming-Hsien YANG, Kun-Hui LIN, Chun-Hao CHOU, Kuo-Cheng LEE
  • Publication number: 20250113539
    Abstract: A method includes forming semiconductive sheets over a substrate and arranged in a vertical direction; forming source/drain regions on either side of each of the semiconductive sheets; forming first air gap inner spacers interleaving with the semiconductive sheets; forming a gate around each of the semiconductive sheets, wherein the first air gap inner spacers are laterally between the gate and a first one of the source/drain regions.
    Type: Application
    Filed: October 3, 2023
    Publication date: April 3, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Yi CHOU, Guan-Lin CHEN, Shi Ning JU, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20250107268
    Abstract: A plurality of holes in a top surface of a silicon medium form a plurality of sub-meta lenses to result in multiple focal points rather than a single point (resulting from using a single meta lens). As a result, optical paths for incoming light are reduced as compared with a single optical path associated with a single meta lens, which in turn reduces angular response of incident photons. Thus, a pixel sensor including the plurality of sub-meta lenses experiences improved light focus and greater signal-to-noise ratio. Additionally, dimensions of the pixel sensor are reduced (particularly a height of the pixel sensor), which allows for greater miniaturization of an image sensor that includes the pixel sensor.
    Type: Application
    Filed: September 22, 2023
    Publication date: March 27, 2025
    Inventors: Yi-Hsuan WANG, Cheng Yu HUANG, Chun-Hao CHUANG, Keng-Yu CHOU, Wen-Hau WU, Wei-Chieh CHIANG, Chih-Kung CHANG
  • Publication number: 20250098343
    Abstract: Various embodiments of the present application are directed towards an image sensor including a wavelength tunable narrow band filter, as well as methods for forming the image sensor. In some embodiments, the image sensor includes a substrate, a first photodetector, a second photodetector, and a filter. The first and second photodetectors neighbor in the substrate. The filter overlies the first and second photodetectors and includes a first distributed Bragg reflector (DBR), a second DBR, and a first interlayer between the first and second DBRs. A thickness of the first interlayer has a first thickness value overlying the first photodetector and a second thickness value overlying the second photodetector. In some embodiments, the filter is limited to a single interlayer. In other embodiments the filter further includes a second interlayer defining columnar structures embedded in the first interlayer and having a different refractive index than the first interlayer.
    Type: Application
    Filed: December 4, 2024
    Publication date: March 20, 2025
    Inventors: Cheng Yu Huang, Chun-Hao Chuang, Kazuaki Hashimoto, Keng-Yu Chou, Wei Chieh Chiang, Wen-Hau Wu, Chih-Kung Chang
  • Publication number: 20250089393
    Abstract: Various embodiments of the present application are directed to a narrow band filter with high transmission and an image sensor comprising the narrow band filter. In some embodiments, the filter comprises a first distributed Bragg reflector (DBR), a second DBR, a defect layer between the first and second DBRs, and a plurality of columnar structures. The columnar structures extend through the defect layer and have a refractive index different than a refractive index of the defect layer. The first and second DBRs define a low transmission band, and the defect layer defines a high transmission band dividing the low transmission band. The columnar structures shift the high transmission band towards lower or higher wavelengths depending upon a refractive index of the columnar structures and a fill factor of the columnar structures.
    Type: Application
    Filed: November 22, 2024
    Publication date: March 13, 2025
    Inventors: Cheng Yu Huang, Chun-Hao Chuang, Chien-Hsien Tseng, Kazuaki Hashimoto, Keng-Yu Chou, Wei-Chieh Chiang, Wen-Hau Wu
  • Publication number: 20250089277
    Abstract: Semiconductor structures and methods are provided. An exemplary method includes depositing forming a first metal-insulator-metal (MIM) capacitor over a substrate and forming a second MIM capacitor over the first MIM capacitor. The forming of the first MIM capacitor includes forming a first conductor plate over a substrate, the first conductor plate comprising a first metal element, conformally depositing a first dielectric layer on the first conductor plate, the first dielectric layer comprising the first metal element, forming a first high-K dielectric layer on the first dielectric layer, conformally depositing a second dielectric layer on the first high-K dielectric layer, the second dielectric layer comprising a second metal element, and forming a second conductor plate over the second dielectric layer, the second conductor plate comprises the second metal element.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 13, 2025
    Inventors: Chia-Yueh Chou, Hsiang-Ku Shen, Chen-Chiu Huang, Dian-Hau Chen, Cheng-Hao Hou, Kun-Yu Lee, Ming-Ho Lin, Alvin Universe Tang, Chun-Hsiu Chiang
  • Patent number: 12243893
    Abstract: A device includes a plurality of photodiode regions within a semiconductor substrate, a plurality of transistors, a plurality of deep trench isolation (DTI) structures, and a plurality of isolation structures. The transistors are over a front-side surface of the semiconductor substrate. The DTI structures extend a first depth from a backside surface of the semiconductor substrate into the semiconductor substrate. The isolation structures extend a second depth from the backside surface of the semiconductor substrate into the semiconductor substrate. The second depth is less than the first depth. From a plan view, each of the plurality of isolation structures has a triangular profile at the backside surface of the semiconductor substrate.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: March 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee
  • Patent number: 12243586
    Abstract: Methods for reading a memory are provided. In response to a first address signal, a first signal is obtained according to first data of the memory and a second signal is obtained according to second data of the memory by a decoding circuit. Binary representation of the first signal is complementary to that of the second signal. A first sensing signal is provided according to a reference signal and the first signal and a second sensing signal is provided according to the reference signal and the second signal by a sensing circuit. An output corresponding to the first sensing signal or the second sensing signal is output in response to a control signal, by an output buffer.
    Type: Grant
    Filed: March 23, 2023
    Date of Patent: March 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yuhsiang Chen, Shao-Yu Chou, Chun-Hao Chang, Min-Shin Wu, Yu-Der Chih
  • Publication number: 20250072052
    Abstract: A device includes a transistor. The transistor includes a plurality of stacked channels, a source/drain region coupled to the stacked channels, and a gate metal wrapped around the stacked channels. The transistor includes a plurality of inner spacers, each inner spacer being positioned laterally between the gate metal and the source/drain region and including a gap and an inner spacer liner layer between the gate metal and the source/drain region.
    Type: Application
    Filed: January 11, 2024
    Publication date: February 27, 2025
    Inventors: Chun Yi CHOU, Guan-Lin CHEN, Shi Ning JU, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Patent number: 12237028
    Abstract: A memory circuit includes a non-volatile memory cell, a comparator and a detection circuit. The comparator is coupled to the non-volatile memory cell, and configured to generate a first output signal. The comparator including a first input terminal and a first output terminal. The first input terminal is coupled to the non-volatile memory cell by a first node, and configured to receive a first voltage. The first output terminal is configured to output the first output signal. The detection circuit is coupled to the comparator and the non-volatile memory cell. The detection circuit is configured to latch the first output signal and disrupt a current path between at least the non-volatile memory cell and the comparator. The detection circuit includes a first inverter coupled to the first output terminal of the comparator and configured to generate an inverted first output signal.
    Type: Grant
    Filed: November 29, 2023
    Date of Patent: February 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Hao Chang, Gu-Huan Li, Shao-Yu Chou
  • Publication number: 20250062166
    Abstract: A semiconductor device includes a first wafer and a second wafer. The semiconductor device includes a seal ring structure comprising a first metal structure in a body of the first wafer, a second metal structure in the body of the first wafer, a third metal structure in a body of the second wafer, and a metal bonding structure including a first set of metal elements coupling the first metal structure and the third metal structure through an interface between the first wafer and the second wafer, and a second set of metal elements coupling the second metal structure and the third metal structure through the interface between the first wafer and the second wafer.
    Type: Application
    Filed: October 31, 2024
    Publication date: February 20, 2025
    Inventors: Chun-Liang LU, Chun-Wei CHIA, Chun-Hao CHOU, Kuo-Cheng LEE
  • Publication number: 20250063833
    Abstract: A semiconductor device according to the present disclosure includes a semiconductor layer, a plurality of metal isolation features disposed in the semiconductor layer, wherein certain of the metal isolation features extend through the substrate to provide for full isolation between adjacent photodetectors and certain of the metal isolation features extend partially through the semiconductor layer to provide partially isolation between adjacent photodetectors.
    Type: Application
    Filed: January 5, 2024
    Publication date: February 20, 2025
    Inventors: Ming-Hsien YANG, Kun-Hui LIN, Chun-Hao CHOU, Kuo-Cheng LEE
  • Patent number: 12224297
    Abstract: A method of making a semiconductor structure includes forming a pixel array region on a substrate. The method further includes forming a first seal ring region on the substrate, wherein the first seal ring region surrounds the pixel array region, and the first seal ring region includes a first seal ring. The method further includes forming a first isolation feature in the first seal ring region, wherein forming the first isolation feature includes filling a first opening with a dielectric material, wherein the first isolation feature is a continuous structure surrounding the pixel array region. The method further includes forming a second isolation feature between the first isolation feature and the pixel array region, wherein forming the second isolation feature includes filling a second opening with the dielectric material.
    Type: Grant
    Filed: January 19, 2023
    Date of Patent: February 11, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yun-Wei Cheng, Chun-Wei Chia, Chun-Hao Chou, Kuo-Cheng Lee, Ying-Hao Chen