Abstract: Semiconductor structures and processes are provided. A semiconductor structure of the present disclosure includes a first base portion and a second base portion extending lengthwise along a first direction, a first source/drain feature disposed over the first base portion, a second source/drain feature disposed over the second base portion, a center dielectric fin sandwiched between the first source/drain feature and the second source/drain feature along a second direction perpendicular to the first direction, and a source/drain contact disposed over the first source/drain feature, the second source/drain feature and the center dielectric fin. A portion of the source/drain contact extends between the first source/drain feature and the second source/drain feature along the second direction.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes channel structures vertically stacked over a substrate and a source/drain structure laterally attached to the channel structures in the first direction. The semiconductor structure also includes a dielectric wall structure laterally attached to the channel structures in the second direction. The second direction is different from the first direction. In addition, the dielectric wall structure includes a bottom portion and a cap layer formed over the bottom portion. The semiconductor structure also includes an isolation feature vertically overlapping the cap layer of the dielectric wall structure and a gate structure formed around the channel structures and covering a sidewall of the isolation feature.

Abstract: The present disclosure provides a multi-state one-time programmable (MSOTP) memory circuit including a memory cell and a programming voltage driving circuit. The memory cell includes a MOS storage transistor, a first MOS access transistor and a second MOS access transistor electrically connected to store two bits of data. When the memory cell is in a writing state, the programming voltage driving circuit outputs a writing control potential to the gate of the MOS storage transistor, and when the memory cell is in a reading state, the programming voltage driving circuit outputs a reading control potential to the gate of the MOS storage transistor.