Patents by Inventor Chun-Heng Liao
Chun-Heng Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240090343Abstract: The present disclosure relates to a magneto-resistive random access memory (MRAM) cell having an extended upper electrode, and a method of formation. In some embodiments, the MRAM cell has a magnetic tunnel junction (MTJ) arranged over a conductive lower electrode. A conductive upper electrode is arranged over the magnetic tunnel junction. Below the conductive lower electrode is a first conductive via structure in a first dielectric layer. Below the conductive via structure is a discrete conductive jumper structure in a second dielectric layer. A dielectric body of a third dielectric material that is different from the first dielectric material and the second dielectric material extends vertical from the first dielectric layer at least partially into the second dielectric layer.Type: ApplicationFiled: November 21, 2023Publication date: March 14, 2024Inventors: Jun-Yao CHEN, Chun-Heng LIAO, Hung Cho WANG
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Patent number: 11856868Abstract: The present disclosure relates to a magneto-resistive random access memory (MRAM) cell having an extended upper electrode, and a method of formation. In some embodiments, the MRAM cell has a magnetic tunnel junction (MTJ) arranged over a conductive lower electrode. A conductive upper electrode is arranged over the magnetic tunnel junction. Below the conductive lower electrode is a first conductive via structure in a first dielectric layer. Below the conductive via structure is a discrete conductive jumper structure in a second dielectric layer. A dielectric body of a third dielectric material that is different from the first dielectric material and the second dielectric material extends vertical from the first dielectric layer at least partially into the second dielectric layer.Type: GrantFiled: May 3, 2022Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jun-Yao Chen, Chun-Heng Liao, Hung Cho Wang
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Patent number: 11785862Abstract: A memory cell with dual sidewall spacers and its manufacturing methods are provided. In some embodiments, the memory cell includes a bottom electrode disposed over a substrate, a resistance switching dielectric disposed over the bottom electrode and having a variable resistance, and a top electrode disposed over the resistance switching dielectric. The memory cell further includes a first sidewall spacer disposed on an upper surface of the bottom electrode and extending upwardly alongside the resistance switching dielectric and the top electrode. The memory cell further includes a second sidewall spacer having a bottom surface disposed on the upper surface of the bottom electrode and directly and conformally lining the first sidewall spacer.Type: GrantFiled: May 13, 2021Date of Patent: October 10, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Heng Liao, Harry-Hak-Lay Chuang, Chang-Jen Hsieh, Hung Cho Wang
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Publication number: 20220263013Abstract: The present disclosure relates to a magneto-resistive random access memory (MRAM) cell having an extended upper electrode, and a method of formation. In some embodiments, the MRAM cell has a magnetic tunnel junction (MTJ) arranged over a conductive lower electrode. A conductive upper electrode is arranged over the magnetic tunnel junction. Below the conductive lower electrode is a first conductive via structure in a first dielectric layer. Below the conductive via structure is a discrete conductive jumper structure in a second dielectric layer. A dielectric body of a third dielectric material that is different from the first dielectric material and the second dielectric material extends vertical from the first dielectric layer at least partially into the second dielectric layer.Type: ApplicationFiled: May 3, 2022Publication date: August 18, 2022Inventors: Jun-Yao CHEN, Chun-Heng LIAO, Hung Cho WANG
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Patent number: 11355696Abstract: The present disclosure relates to a magneto-resistive random access memory (MRAM) cell having an extended upper electrode, and a method of formation. In some embodiments, the MRAM cell has a magnetic tunnel junction (MTJ) arranged over a conductive lower electrode. A conductive upper electrode is arranged over the magnetic tunnel junction. Below the conductive lower electrode is a first conductive via structure in a first dielectric layer. Below the conductive via structure is a discrete conductive jumper structure in a second dielectric layer. A dielectric body of a third dielectric material that is different from the first dielectric material and the second dielectric material extends vertical from the first dielectric layer at least partially into the second dielectric layer.Type: GrantFiled: June 12, 2020Date of Patent: June 7, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jun-Yao Chen, Chun-Heng Liao, Hung Cho Wang
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Patent number: 11283009Abstract: A method for manufacturing a memory device is provided. The method includes forming a bottom electrode layer, a resistance switching element layer over the bottom electrode layer, and a top electrode layer over the resistance switching element layer; patterning the top electrode layer into a top electrode; forming a protection spacer on a sidewall of the top electrode; patterning the resistance switching element layer into a resistance switching element after forming the protection spacer; and patterning the bottom electrode layer into a bottom electrode after patterning the resistance switching element layer.Type: GrantFiled: December 3, 2019Date of Patent: March 22, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Harry-Hak-Lay Chuang, Chun-Heng Liao, Jun-Yao Chen, Hung-Cho Wang
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Publication number: 20210391530Abstract: The present disclosure relates to a magneto-resistive random access memory (MRAM) cell having an extended upper electrode, and a method of formation. In some embodiments, the MRAM cell has a magnetic tunnel junction (MTJ) arranged over a conductive lower electrode. A conductive upper electrode is arranged over the magnetic tunnel junction. Below the conductive lower electrode is a first conductive via structure in a first dielectric layer. Below the conductive via structure is a discrete conductive jumper structure in a second dielectric layer. A dielectric body of a third dielectric material that is different from the first dielectric material and the second dielectric material extends vertical from the first dielectric layer at least partially into the second dielectric layer.Type: ApplicationFiled: June 12, 2020Publication date: December 16, 2021Inventors: Jun-Yao CHEN, Chun-Heng LIAO, Hung Cho WANG
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Publication number: 20210280773Abstract: A memory cell with dual sidewall spacers and its manufacturing methods are provided. In some embodiments, the memory cell includes a bottom electrode disposed over a substrate, a resistance switching dielectric disposed over the bottom electrode and having a variable resistance, and a top electrode disposed over the resistance switching dielectric. The memory cell further includes a first sidewall spacer disposed on an upper surface of the bottom electrode and extending upwardly alongside the resistance switching dielectric and the top electrode. The memory cell further includes a second sidewall spacer having a bottom surface disposed on the upper surface of the bottom electrode and directly and conformally lining the first sidewall spacer.Type: ApplicationFiled: May 13, 2021Publication date: September 9, 2021Inventors: Chun-Heng Liao, Harry-Hak-Lay Chuang, Chang-Jen Hsieh, Hung Cho Wang
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Patent number: 11031543Abstract: A memory cell with dual sidewall spacers and its manufacturing methods are provided. In some embodiments, a multi-layer stack is formed and patterned to form a hard mask, a top electrode and a resistance switching dielectric. Then, a first dielectric spacer layer is formed over the bottom electrode layer, extending alongside the resistance switching dielectric, the top electrode, and the hard mask, and further extending over the hard mask. Then, a second dielectric spacer layer is formed directly on and conformally lining the first dielectric spacer layer. The first dielectric spacer layer is deposited at a first temperature and the second dielectric spacer layer is deposited at a second temperature higher than that of the first temperature.Type: GrantFiled: May 15, 2019Date of Patent: June 8, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Heng Liao, Harry-Hak-Lay Chuang, Chang-Jen Hsieh, Hung Cho Wang
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Publication number: 20210098693Abstract: A method for manufacturing a memory device is provided. The method includes forming a bottom electrode layer, a resistance switching element layer over the bottom electrode layer, and a top electrode layer over the resistance switching element layer; patterning the top electrode layer into a top electrode; forming a protection spacer on a sidewall of the top electrode; patterning the resistance switching element layer into a resistance switching element after forming the protection spacer; and patterning the bottom electrode layer into a bottom electrode after patterning the resistance switching element layer.Type: ApplicationFiled: December 3, 2019Publication date: April 1, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Harry-Hak-Lay CHUANG, Chun-Heng LIAO, Jun-Yao CHEN, Hung-Cho WANG
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Publication number: 20200127189Abstract: A memory cell with dual sidewall spacers and its manufacturing methods are provided. In some embodiments, a multi-layer stack is formed and patterned to form a hard mask, a top electrode and a resistance switching dielectric. Then, a first dielectric spacer layer is formed over the bottom electrode layer, extending alongside the resistance switching dielectric, the top electrode, and the hard mask, and further extending over the hard mask. Then, a second dielectric spacer layer is formed directly on and conformally lining the first dielectric spacer layer. The first dielectric spacer layer is deposited at a first temperature and the second dielectric spacer layer is deposited at a second temperature higher than that of the first temperature.Type: ApplicationFiled: May 15, 2019Publication date: April 23, 2020Inventors: Chun-Heng Liao, Harry-Hak-Lay Chuang, Chang-Jen Hsieh, Hung Cho Wang
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Patent number: 9893278Abstract: The present disclosure relates an integrated circuit (IC). The IC comprises a memory region and a logic region. A lower metal layer is disposed over a substrate, and comprises a first lower metal line within the memory region. An upper metal layer overlies the lower metal layer, and comprises a first upper metal line within the memory region. A memory cell is disposed between the first lower metal line and the first upper metal line, and comprises a planar bottom electrode. The planar bottom electrode abuts a first lower metal via of the lower metal layer. By forming the planar bottom electrode and connecting the planar bottom electrode to the lower metal layer through the lower metal via, no additional BEVA planarization and/or patterning processes are needed. As a result, risk of damaging the lower metal lines are reduced, thereby providing more reliable read/write operations and/or better performance.Type: GrantFiled: August 8, 2016Date of Patent: February 13, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Harry-Hak-Lay Chuang, Chun-Heng Liao
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Publication number: 20180040817Abstract: The present disclosure relates an integrated circuit (IC). The IC comprises a memory region and a logic region. A lower metal layer is disposed over a substrate, and comprises a first lower metal line within the memory region. An upper metal layer overlies the lower metal layer, and comprises a first upper metal line within the memory region. A memory cell is disposed between the first lower metal line and the first upper metal line, and comprises a planar bottom electrode. The planar bottom electrode abuts a first lower metal via of the lower metal layer. By forming the planar bottom electrode and connecting the planar bottom electrode to the lower metal layer through the lower metal via, no additional BEVA planarization and/or patterning processes are needed. As a result, risk of damaging the lower metal lines are reduced, thereby providing more reliable read/write operations and/or better performance.Type: ApplicationFiled: August 8, 2016Publication date: February 8, 2018Inventors: Harry-Hak-Lay Chuang, Chun-Heng Liao
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Patent number: 9634243Abstract: The present disclosure provides a semiconductor structure, including a logic region and a memory region adjacent to the logic region. The memory region includes a first Nth metal line of an Nth metal layer, a magnetic tunneling junction (MTJ) over first Nth metal line, and a first (N+1)th metal via of an (N+1)th metal layer, the first (N+1)th metal via being disposed over the MTJ layer. N is an integer greater than or equal to 1. A method of manufacturing the semiconductor structure is also disclosed.Type: GrantFiled: November 27, 2015Date of Patent: April 25, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Harry-Hak-Lay Chuang, Chun-Heng Liao
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Patent number: 9537016Abstract: A memory device is disclosed. The memory device includes a substrate, including a substrate, including a source region and a drain region; and a gate stack, formed over a surface of the substrate, wherein the gate stack includes: a tunneling layer; a first layer; a second layer; a third layer; and a blocking layer; wherein each of the tunneling layer and the blocking layer has an oxygen proportion higher than the first, the second and the third layers; the first layer has a highest silicon proportion among the first, the second and the third layers; the second layer has a highest oxygen proportion among the first, the second and the third layers; and the first layer has a highest nitrogen proportion among the first, the second and the third layers. An associated gate stack and a manufacturing method are also disclosed.Type: GrantFiled: February 3, 2016Date of Patent: January 3, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hau-Yan Lu, Chun-Yao Ko, Chun-Heng Liao, Felix Ying-Kit Tsui
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Patent number: 9269758Abstract: The present disclosure involves a method. The method includes providing a substrate including a top surface. The method also includes forming a gate over the top surface of the substrate. The formed gate has a first height measured from the top surface of the substrate. The method also includes etching the gate to reduce the gate to a second height. This second height is substantially less than the first height. The present disclosure also involves a semiconductor device. The semiconductor device includes a substrate. The substrate includes a top surface. The semiconductor device also includes a first gate formed over the top surface of the substrate. The first gate has a first height. The semiconductor device also includes a second gate formed over the top surface of the substrate. The second gate has a second height. The first height is substantially less than the second height.Type: GrantFiled: January 13, 2011Date of Patent: February 23, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jing-Hwang Yang, Chun-Heng Liao, Hsin-Li Cheng, Liang-Kai Han
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Publication number: 20120181612Abstract: The present disclosure involves a method. The method includes providing a substrate including a top surface. The method also includes forming a gate over the top surface of the substrate. The formed gate has a first height measured from the top surface of the substrate. The method also includes etching the gate to reduce the gate to a second height. This second height is substantially less than the first height. The present disclosure also involves a semiconductor device. The semiconductor device includes a substrate. The substrate includes a top surface. The semiconductor device also includes a first gate formed over the top surface of the substrate. The first gate has a first height. The semiconductor device also includes a second gate formed over the top surface of the substrate. The second gate has a second height. The first height is substantially less than the second height.Type: ApplicationFiled: January 13, 2011Publication date: July 19, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jing-Hwang Yang, Chun-Heng Liao, Hsin-Li Cheng, Liang-Kai Han