Abstract: A method for fabricating a crown capacitor includes: forming a first supporting layer over a substrate; forming a second supporting layer above the first supporting layer; alternately stacking first and second sacrificial layers between the first and second supporting layers to collectively form a stacking structure; forming a recess extending through the stacking structure; performing an etching process to the first sacrificial layers at a first etching rate and the second sacrificial layers at a second etching rate greater than the first etching rate, such that each second sacrificial layer and immediately-adjacent two of the first sacrificial layers collectively define a concave portion; forming a first electrode layer over a surface of the recess in which the first electrode layer has a wavy structure; removing the first and second sacrificial layers; and forming a dielectric layer and a second electrode layer over the first electrode layer.

Abstract: A method for fabricating a crown capacitor includes: forming a first supporting layer over a substrate; forming a second supporting layer above the first supporting layer; alternately stacking first and second sacrificial layers between the first and second supporting layers to collectively form a stacking structure; forming a recess extending through the stacking structure; performing an etching process to the first sacrificial layers at a first etching rate and the second sacrificial layers at a second etching rate greater than the first etching rate, such that each second sacrificial layer and immediately-adjacent two of the first sacrificial layers collectively define a concave portion; forming a first electrode layer over a surface of the recess in which the first electrode layer has a wavy structure; removing the first and second sacrificial layers; and forming a dielectric layer and a second electrode layer over the first electrode layer.

Abstract: A method of forming semiconductor structure includes forming a dielectric stack over a substrate. A mask layer is formed over the dielectric stack. A first opening is formed in the mask layer to expose dielectric stack. A second opening is formed in the dielectric stack to expose the substrate, wherein the second opening is communicated with the first opening. A fill layer is formed in the first opening and the second opening. The mask layer and the fill layer are removed such that sidewalls of the dielectric stack are exposed. A capacitor is formed in the second opening of the dielectric stack.

Abstract: The present application discloses a semiconductor device. The semiconductor device includes a package structure including a first side and a second side opposite to the first side; an interposer structure positioned over the first side of the package structure; a first die positioned over the interposer structure; a second die positioned over the interposer structure; and a plurality of bottom interconnectors positioned on the second side of the package structure, and respectively including: a bottom exterior layer positioned on the second side of the package structure; a bottom interior layer enclosed by the bottom exterior layer; and a cavity enclosed by the bottom interior layer.

Abstract: The present disclosure provides to a semiconductor memory device. The semiconductor memory device includes a substrate having a cell area and a peripheral area; and a first bit line structure disposed on and protruding from a surface of the cell area. The first bit line structure is sandwiched by a pair of air gaps and a barrier layer is conformally overlaying the air gaps adjacent to the sidewalls of the first bit line structure and the cell area. The first bit line structure has a sidewall and an ascending top portion, and a landing pad is disposed over the ascending top portion and the sidewalls of the first bit line structure. The landing pad has an inclined surface corresponding to the ascending top portion of the first bit line structure.

Abstract: The disclosure provides a pattern collapse free wet clean process for fabricating semiconductor devices. By performing post reactive ion etching (RIE) using a fluorine-containing gas such as C2F6, followed by cleaning in a single wafer cleaner (SWC) with diluted hydrofluoric acid (HF) or in a solution of ammonia and HF, a substrate with multiple pattern collapse free high aspect ratio shallow trench isolation (STI) features can be obtained.

Abstract: The present disclosure provides to a method for manufacturing a semiconductor memory device. The method includes receiving a substrate including a cell area and a peripheral area; forming a first bit line structure on a surface of the cell area; depositing a landing pad above the barrier layer and on the top surface of the first bit line structure; removing a top corner of the landing pad to form an inclined surface connecting a top surface of the landing pad to a sidewall of the landing pad; etching the nitride layer of the first bit line structure and the spacer nitride layer from the top opening so as to form a concavity; etching the spacer oxide layer from the concavity to form an air gap; and depositing a silicon nitride layer to seal the air gap.

Abstract: The present application discloses a semiconductor device. The semiconductor device includes a package structure including a first side and a second side opposite to the first side; an interposer structure positioned over the first side of the package structure; a first die positioned over the interposer structure; a second die positioned over the interposer structure; and a plurality of bottom interconnectors positioned on the second side of the package structure, and respectively including: a bottom exterior layer positioned on the second side of the package structure; a bottom interior layer enclosed by the bottom exterior layer; and a cavity enclosed by the bottom interior layer.

Abstract: A method for manufacturing a capacitor includes: providing a substrate and a multilayer structure; forming a recess in the multilayer structure; forming a first electrode layer on a surface of the recess; performing a selective etching treatment to remove the first and second stack material layers; performing a selective vapor phase etching treatment to the first electrode layer to form a smaller thickness of the first electrode layer; and forming a dielectric layer and a second electrode layer in which the dielectric layer is between the first and second electrode layer.

Abstract: The present disclosure provides to a semiconductor memory device. The semiconductor memory device includes a substrate having a cell area and a peripheral area; and a first bit line structure disposed on and protruding from a surface of the cell area. The first bit line structure is sandwiched by a pair of air gaps and a barrier layer is conformally overlaying the air gaps adjacent to the sidewalls of the first bit line structure and the cell area. The first bit line structure has a sidewall and an ascending top portion, and a landing pad is disposed over the ascending top portion and the sidewalls of the first bit line structure. The landing pad has an inclined surface corresponding to the ascending top portion of the first bit line structure.

Abstract: The present disclosure provides to a method for manufacturing a semiconductor memory device. The method includes receiving a substrate including a cell area and a peripheral area; forming a first bit line structure on a surface of the cell area; depositing a landing pad above the barrier layer and on the top surface of the first bit line structure; removing a top corner of the landing pad to form an inclined surface connecting a top surface of the landing pad to a sidewall of the landing pad; etching the nitride layer of the first bit line structure and the spacer nitride layer from the top opening so as to form a concavity; etching the spacer oxide layer from the concavity to form an air gap; and depositing a silicon nitride layer to seal the air gap.

Abstract: The present disclosure provides a method for fabricating a semiconductor device with a carbon liner over a gate structure. The method includes forming a first gate structure over a semiconductor substrate; forming a first source/drain region in the semiconductor substrate, wherein the first source/drain region is adjacent to the first gate structure; conformally depositing a carbon liner over the first gate structure and the semiconductor substrate; forming a dielectric layer over the carbon liner; and forming a bit line contact penetrating through the dielectric layer and the carbon liner, wherein the bit line contact is electrically connected to the first source/drain region, and wherein the bit line contact is separated from the first gate structure by the carbon liner.

Abstract: A for preparing a semiconductor device includes forming a first dielectric layer over a semiconductor substrate, and forming an etch stop layer over the first dielectric layer. The method also includes forming a second dielectric layer over the etch stop layer, and forming a first metal plug penetrating through the second dielectric layer, the etch stop layer and the first dielectric layer. The first metal plug protrudes from the second dielectric layer. The method further includes performing an anisotropic etching process to partially remove the first metal plug such that the first metal plug has a convex top surface, and forming a third dielectric layer covering the second dielectric layer and the convex top surface of the first metal plug. In addition, the method includes forming a second metal plug over the first metal plug.

Abstract: The disclosure provides a semiconductor structure comprising a plurality of bit line structures and a method for manufacturing the same. In the present disclosure, by allowing at least one of the bit line structures to have a width at its top less than a width at its bottom, the semiconductor structure may have an increased total tungsten volume. The contact surface between the bit line structures and the landing pad is increased, so the landing pad resistance can be decreased. Therefore, the performance of the semiconductor structure can be enhanced.

Abstract: The disclosure provides a pattern collapse free wet clean process for fabricating semiconductor devices. By performing post reactive ion etching (RIE) using a fluorine-containing gas such as C2F6, followed by cleaning in a single wafer cleaner (SWC) with diluted hydrofluoric acid (HF) or in a solution of ammonia and HF, a substrate with multiple pattern collapse free high aspect ratio shallow trench isolation (STI) features can be obtained.

Abstract: The present disclosure relates to a FinFET structure and a method of manufacturing the same. The FinFET structure includes a first fin and a second fin. The first fin is over a first base and has a first channel region. The first channel region has a first channel length. The second fin is over a second base and has a second channel region. The second channel region has a second channel length. The second channel length is different from the first channel length.

Abstract: The present disclosure provides a semiconductor structure having a memory structure and a method for manufacturing the semiconductor structure. The semiconductor structure includes a first layer, a second layer over the first layer, a third layer over the second layer, and a trench capacitor. The trench capacitor is disposed in a trench penetrating the first layer, the second layer, and the third layer. The trench capacitor includes a bottom metal layer, a middle insulating layer, and a top metal layer. The bottom metal layer covers a side wall of the first layer, a side wall of the second layer, and a first portion of a side wall of the third layer. The middle insulating layer covers the bottom metal layer and a second portion of the side wall of the third layer. The top metal layer covers the middle insulating layer.

Abstract: The present disclosure provides a semiconductor structure having a memory structure and a method for manufacturing the semiconductor structure. The semiconductor structure includes a first layer, a second layer over the first layer, a third layer over the second layer, and a trench capacitor. The trench capacitor is disposed in a trench penetrating the first layer, the second layer, and the third layer. The trench capacitor includes a bottom metal layer, a middle insulating layer, and a top metal layer. The bottom metal layer covers a side wall of the first layer, a side wall of the second layer, and a first portion of a side wall of the third layer. The middle insulating layer covers the bottom metal layer and a second portion of the side wall of the third layer. The top metal layer covers the middle insulating layer.

Abstract: A method for fabricating a crown capacitor includes: forming a first supporting layer over a substrate; forming a second supporting layer above the first supporting layer; alternatively stacking first and second sacrificial layers between the first and second supporting layers to collectively form a stacking structure; forming a recess extending through the stacking structure; performing an etching process to the first sacrificial layers at a first etching rate and the second sacrificial layers at a second etching rate greater than the first etching rate, such that each second sacrificial layer and immediately-adjacent two of the first sacrificial layers collectively define a concave portion; forming a first electrode layer over a surface of the recess in which the first electrode layer has a wavy structure; removing the first and second sacrificial layers; and forming a dielectric layer and a second electrode layer over the first electrode layer.