Patents by Inventor Chun-Hsiang Chen
Chun-Hsiang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11990507Abstract: A high voltage transistor structure including a substrate, a first isolation structure, a second isolation structure, a gate structure, a first source and drain region, and a second source and drain region is provided. The first isolation structure and the second isolation structure are disposed in the substrate. The gate structure is disposed on the substrate, at least a portion of the first isolation structure, and at least a portion of the second isolation structure. The first source and drain region and the second source and drain region are located in the substrate on two sides of the first isolation structure and the second isolation structure. The depth of the first isolation structure is greater than the depth of the second isolation structure.Type: GrantFiled: August 16, 2021Date of Patent: May 21, 2024Assignee: United Microelectronics Corp.Inventors: Chin-Hung Chen, Ssu-I Fu, Chih-Kai Hsu, Chun-Ya Chiu, Chia-Jung Hsu, Yu-Hsiang Lin
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Patent number: 11986376Abstract: The present disclosure provides a dressing configured to cover a wound. The dressing includes a substrate layer, a contact layer and a readable pattern layer. The substrate layer is light-permeable. The contact layer is located at a side of the substrate layer, and the contact layer is configured to contact the wound or skin around the wound. The readable pattern layer is disposed on the contact layer. The readable pattern layer includes a plurality of positioning marks and a plurality of colored cells. The positioning marks are configured to define an information area. The colored cells are located in the information areas, wherein at least part of the colored cells includes a biological indicator, and the positioning marks and the colored cells are visible through the substrate layer.Type: GrantFiled: June 6, 2021Date of Patent: May 21, 2024Assignee: CYMMETRIK ENTERPRISE CO., LTD.Inventors: Sz-Hau Chen, Chun-Hsiang Yang
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Publication number: 20240164062Abstract: A heat dissipation device of electronic equipment has a base, a heat dissipation group, and a cover. The base has an opening, a chamber, and a boss formed in the chamber. The heat dissipation group is connected to the base and has a circuit board and a cooling blade. The circuit board is mounted in the chamber, abuts against the boss, and has a heat source area and at least one non-heat-source area. The heat source area has a first surface facing the boss and a second surface facing the opening. The cooling blade is connected to the base and is located at the second surface. The first surface and the second surface of the heat source area respectively correspond to the boss and the cooling blade in location to provide a guiding direction for heat conduction. The cover is connected to the base.Type: ApplicationFiled: November 10, 2022Publication date: May 16, 2024Inventors: Fu Hsiang Chung, Hong Fang Chen, Chun Tse Chan
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Publication number: 20240154642Abstract: The present disclosure provides an electronic module including a circuit including a transmitting part and a receiving part physically separated from the transmitting part. The electronic module also includes an element isolated from the circuit and configured to block electrical interference between the transmitting part and the receiving part.Type: ApplicationFiled: January 16, 2024Publication date: May 9, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Shih-Wen LU, Chun-Jen CHEN, Po-Hsiang TSENG, Hsin-Han LIN, Ming-Lun YU
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Publication number: 20240137709Abstract: An electro-acoustical transducer device is disclosed, which includes: a hollow disk body that generally defines an axis of propagation, the hollow disk body comprising: a pair of plate members extending substantially perpendicular to the axis of propagation, each provided with a central transmitting port arranged about the axis of propagation, and a peripheral enclosure jointing the pair of plate members at the respective outer edge portions thereof, thereby defining a chamber of resonance between the pair of plate members; wherein a ring-opening about the axis of propagation that enables access to the chamber of resonance is formed between the central transmitting ports of the plate members.Type: ApplicationFiled: April 27, 2023Publication date: April 25, 2024Inventors: YU-CHEN CHEN, CHUN-KAI CHAN, HSU-HSIANG CHENG, MING-CHING CHENG
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Publication number: 20240131010Abstract: In some embodiments of the present disclosure, a sustained release osmotic-controlled pharmaceutical composition is provided, including: a core and a semi-permeable membrane coated on the core. The core includes a drug compartment, in which the drug compartment includes a first active ingredient, a first polymer and a first osmogen, and the first active ingredient includes lurasidone, a pharmaceutical acceptable salt of the lurasidone or a combination thereof. The semi-permeable membrane includes a membrane body and at least one pore distributed in the membrane body.Type: ApplicationFiled: October 15, 2023Publication date: April 25, 2024Inventors: Chun-You LIOU, Tzu-Hsien CHAN, Hua-Jing JHAN, I-Hsiang LIU, Tse-Hsien CHEN, Chi-Heng JIAN
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Patent number: 11964358Abstract: A method includes placing a polisher head on platen, the polisher head including a set of first magnets, and controlling a set of second magnets to rotate the polisher head on the platen, wherein controlling the set of second magnets includes reversing the polarity of at least one second magnet of the set of second magnets to produce a magnetic force on at least one first magnet of the set of first magnets, wherein the set of second magnets are external to the polisher head.Type: GrantFiled: March 19, 2021Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shang-Yu Wang, Chun-Hao Kung, Ching-Hsiang Tsai, Kei-Wei Chen, Hui-Chi Huang
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Publication number: 20240128127Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, an isolation structure on the SDB structure, a first spacer adjacent to the isolation structure, a metal gate adjacent to the isolation structure, a shallow trench isolation (STI around the fin-shaped structure, and a second isolation structure on the STI. Preferably, a top surface of the first spacer is lower than a top surface of the isolation structure and a bottom surface of the first spacer is lower than a bottom surface of the metal gate.Type: ApplicationFiled: December 28, 2023Publication date: April 18, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chih-Kai Hsu, Ssu-l Fu, Chun-ya Chiu, Chi-Ting Wu, Chin-HUNG Chen, Yu-Hsiang Lin
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Patent number: 11963385Abstract: The disclosure provides a local stretch packaging structure, including a substrate, a flexible electronic element, a plurality of light-emitting display elements, and a packaging layer. The flexible electronic element is disposed on the substrate. These light-emitting display elements are disposed on the flexible electronic element. The packaging layer includes a packaging area and a non-packaging area. The packaging area covers the upper surface and sidewalls of these light-emitting display elements. The non-packaging area is directly covered the flexible electronic element that is not disposed with these light-emitting display elements.Type: GrantFiled: October 25, 2021Date of Patent: April 16, 2024Assignees: Interface Technology (ChengDu) Co., Ltd., Interface Optoelectronics (ShenZhen) Co., Ltd., General Interface Solution LimitedInventors: Wen-You Lai, Ping-Hsiang Kao, Po-Lun Chen, Chun-Ta Chen, Po-Ching Lin, Ya-Chu Hsu
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Publication number: 20240120162Abstract: A key structure is provided. The key structure includes an elastic element and a keycap disposed on the elastic element. The elastic element includes a movable portion, a fixed portion and a connection portion. The fixed portion surrounds the movable portion. The connection portion connects the fixed portion with the movable portion. The keycap includes a first connection portion. The first connection portion is connected to the fixed portion or the movable portion.Type: ApplicationFiled: September 28, 2023Publication date: April 11, 2024Inventors: Ko-Hsiang LIN, Chun-Lin CHEN
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Publication number: 20240096861Abstract: A semiconductor package assembly is provided. The semiconductor package assembly includes first semiconductor die, a second semiconductor die and a memory package. The first semiconductor die and the second semiconductor die are stacked on each other. The first semiconductor die includes a first interface and a third interface. The first interface overlaps and is electrically connected to the second interface arranged on the second semiconductor die. The third interface is arranged on a first edge of the first semiconductor die. The memory package is disposed beside the first semiconductor die, wherein the memory package is electrically connected to the first semiconductor die by the third interface.Type: ApplicationFiled: August 23, 2023Publication date: March 21, 2024Inventors: Che-Hung KUO, Hsiao-Yun CHEN, Wen-Pin CHU, Chun-Hsiang HUANG
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Publication number: 20240096781Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.Type: ApplicationFiled: March 20, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Ti Lu, Hao-Yi Tsai, Chia-Hung Liu, Yu-Hsiang Hu, Hsiu-Jen Lin, Tzuan-Horng Liu, Chih-Hao Chang, Bo-Jiun Lin, Shih-Wei Chen, Hung-Chun Cho, Pei-Rong Ni, Hsin-Wei Huang, Zheng-Gang Tsai, Tai-You Liu, Po-Chang Shih, Yu-Ting Huang
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Patent number: 11935894Abstract: An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.Type: GrantFiled: November 4, 2022Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fong-yuan Chang, Chun-Chen Chen, Po-Hsiang Huang, Lee-Chung Lu, Chung-Te Lin, Jerry Chang Jui Kao, Sheng-Hsiung Chen, Chin-Chou Liu
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Publication number: 20240088293Abstract: An n-type metal oxide semiconductor transistor includes a gate structure, two source/drain regions, two amorphous portions and a silicide. The gate structure is disposed on a substrate. The two source/drain regions are disposed in the substrate and respectively located at two sides of the gate structure, wherein at least one of the source/drain regions is formed with a dislocation. The two amorphous portions are respectively disposed in the two source/drain regions. The silicide is disposed on the two source/drain regions, wherein at least one portion of the silicide overlaps the two amorphous portions.Type: ApplicationFiled: October 5, 2022Publication date: March 14, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chun-Ya Chiu, Ssu-I Fu, Chin-Hung Chen, Jin-Yan Chiou, Wei-Chuan Tsai, Yu-Hsiang Lin
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Patent number: 11925457Abstract: A device for encouraging and guiding a spirometer user includes a housing, a main valve, a visual assembly, and a sound making assembly. The housing has a guiding channel, a first outlet channel, a second outlet channel, and an inlet channel. The main valve is disposed in a housing communicating with the guiding channel, the first outlet channel, the second outlet channel or the inlet channel and configured to regulate or control fluid flowing paths. The visual assembly includes a check valve in the second outlet channel, and at least one movable member. The sound making assembly includes a check valve and a sound maker. So, it can generate the visual and sound encouraging effects for learning how to use a spirometer correctly.Type: GrantFiled: February 17, 2021Date of Patent: March 12, 2024Assignees: TAICHUNG VETERANS GENERAL HOSPITAL, CENTRAL TAIWAN UNIVERSITY OF SCIENCE AND TECHNOLOGYInventors: Ming-Feng Wu, Yu-Hsuan Chen, Kuo-Chih Su, Chun-Hsiang Wang
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Publication number: 20240069608Abstract: The present application provides a graphics card expansion device. The graphics card expansion device includes a main chassis and an expansion chassis. The expansion chassis comprises: at least one graphics card storage box, the at least one graphics card storage box is equipped with at least one graphics card; at least one second power source, the at least second power source provides power to at least one graphics card in the at least one graphics card storage box; at least one adapter card, the at least one graphics card storage box communicates with the motherboard in the main box through the at least one adapter card.Type: ApplicationFiled: August 22, 2023Publication date: February 29, 2024Inventors: CHING-JOU CHEN, WEN-HSIANG HUNG, CHUN-BAO GU
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Publication number: 20230369431Abstract: A semiconductor structure and a method for manufacturing a semiconductor structure are provided. The semiconductor structure includes: a substrate; a gate trench located in the substrate; a gate oxide layer located on a side wall and a bottom of the gate trench; and a gate conductive layer located on a surface of the gate oxide layer, a top of the gate conductive layer being lower than a top of the gate trench. The gate oxide layer includes an ion implantation area. A bottom of the ion implantation area is higher than a bottom of the gate conductive layer and lower than the top of the gate conductive layer, and a top of the ion implantation area is higher than or flush with the top of the gate conductive layer.Type: ApplicationFiled: August 24, 2022Publication date: November 16, 2023Inventors: WEI CHANG, CHUN-HSIANG CHEN, Zhaohong LV, Yongchang ZHUO, TIEH-CHIANG WU
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Patent number: 8894777Abstract: A surface treatment method of a magnesium alloy article includes, instead of forming a primer on a magnesium alloy based composite first, directly performing a hairline finish process on the magnesium alloy based composite, to form a hairline structure on a surface of the magnesium alloy based composite, and performing a chemical oxidation process on the magnesium alloy based composite, to form a glossy film covering the hairline structure on the magnesium alloy based composite, thereby forming a magnesium alloy article structure. Alternatively, another chemical oxidation process is performed before the hairline finish process, to form an oxide film on the surface of the magnesium alloy based composite.Type: GrantFiled: September 25, 2011Date of Patent: November 25, 2014Assignee: Getac Technology CorporationInventor: Chun-Hsiang Chen
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Publication number: 20120125487Abstract: A surface treatment method of a magnesium alloy article includes, instead of forming a primer on a magnesium alloy based composite first, directly performing a hairline finish process on the magnesium alloy based composite, to form a hairline structure on a surface of the magnesium alloy based composite, and performing a chemical oxidation process on the magnesium alloy based composite, to form a glossy film covering the hairline structure on the magnesium alloy based composite, thereby forming a magnesium alloy article structure. Alternatively, another chemical oxidation process is performed before the hairline finish process, to form an oxide film on the surface of the magnesium alloy based composite.Type: ApplicationFiled: September 25, 2011Publication date: May 24, 2012Applicant: GETAC TECHNOLOGY CORPORATIONInventor: Chun-Hsiang CHEN
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Patent number: D1024932Type: GrantFiled: March 10, 2022Date of Patent: April 30, 2024Assignee: WALSIN LIHWA CORPORATIONInventors: Ko-Ming Chen, Shih-Hsiang Wang, An-Hung Lin, Min-Chuan Wu, Shao-Pei Lin, Chien-Chung Ni, Chun-Ying Lin