Abstract: The disclosure provides a recommended method for replacing equipment and an electronic device. A plurality of reference electricity consumptions of an equipment are estimated by using an electricity consumption prediction model based on equipment operation information of the equipment in a plurality of unit periods. A plurality of actual electricity consumptions of the equipment in the multiple unit periods are obtained. An abnormal electricity consumption time interval is determined by comparing the actual electricity consumptions with the reference electricity consumptions. A replacement index and an equipment energy efficiency of the equipment in the abnormal electricity consumption time interval are determined according to the equipment operation information of the equipment in the abnormal electricity consumption time interval.

Abstract: A thermoplastic fiber composite film manufacturing mechanism and method are provided. The mechanism includes a substrate outputting module, a fiber material outputting module, and a pressing module. The substrate outputting module continuously outputs a film-shaped molten plastic substrate along an output direction. The fiber material outputting module is disposed on one side of the substrate outputting module. The fiber material outputting module continuously outputs a fiber sheet material. The pressing module is disposed on one side of the fiber material outputting module away from the substrate outputting module. The pressing module has a first and a second rollers neighboring each other, with a pressing area formed therebetween. The plastic substrate and the fiber sheet material move to the pressing area; the first and second rollers press the plastic substrate and the fiber sheet material together in parallel into a composite film.

Abstract: A nanowire transistor includes a channel structure on a substrate, a gate structure on and around the channel structure, a source/drain structure adjacent to two sides of the gate structure, and a contact plug connected to the source/drain structure. Preferably, the source/drain structure includes graphene and the contact plug further includes a silicide layer on the source/drain structure, a graphene layer on the silicide layer, and a barrier layer on the graphene layer.

Abstract: A method for producing a porous structure electrode with gas permeability and liquid impermeability, includes the following steps: Step 1: mixing a catalytic material having hydrophilicity, a carbon nanotube material, a material with a hydrophilic group, and a carbon black material to form a first slurry, wherein the carbon nanotube material has a specific surface area equal to or greater than the carbon black material; Step 2: mixing the first slurry with an emulsified material to form a second slurry; Step 3: obtaining a film material through a film forming process; Step 4: heating the film material to a first temperature to remove solvent in the film material; Step 5: Repeating steps 3 to 4; and Step 6: heating the film material to a second temperature to remove liquid in the film material, thereby leaving pores in the film material, and allowing the film material to solidify.

Abstract: A manufacturing method of a circuit carrier includes the following. A fine redistribution structure is formed on a temporary substrate. A build-up package substrate is provided. The build-up package substrate includes a substrate, a first build-up circuit structure, and a second build-up circuit structure. The first build-up circuit structure is disposed on a top surface of the substrate. The second build-up circuit structure is disposed on a bottom surface of the substrate. The fine redistribution structure is bonded on the build-up package substrate. The fine redistribution structure is directly attached on the first build-up circuit structure. A line width and a line spacing of the fine redistribution structure are smaller than a line width and a line spacing of the first build-up circuit structure. At least one conductive through hole is formed to penetrate the fine redistribution structure and a portion of the first build-up circuit structure.

Abstract: The invention provides a semiconductor layout pattern including high-voltage devices, which comprises a substrate, wherein a high-voltage device region and an MRAM (magnetic random access memory) region are adjacent to each other, wherein the MRAM region at least comprises a plurality of MRAM cells arranged in an array, wherein each MRAM cell comprises two fin structures parallel to each other and arranged along an X direction, and two gate structures parallel to each other and arranged along a Y direction. A drain metal layer is located between the two gate structures, two source metal layers are located on the other side of the two gate structures, respectively, and an MTJ (magnetic tunneling junction) element is electrically connected with the drain metal layers.

Abstract: An energy-saving prediction method for factory electricity consumption and an electronic apparatus are provided. The method includes the following steps. A reference electricity consumption amount in a unit period is predicted based on factory actual operation information in the unit period by using an electricity consumption prediction model. An actual electricity consumption amount in the unit period is acquired. The reference electricity consumption amount and the actual electricity consumption amount are displayed on an electricity consumption reference interface. A function is provided according to a first difference value between the reference electricity consumption amount and the actual electricity consumption amount.

Abstract: A button module includes a first electronic element, a pressing element, a second electronic element, and an operation element. The pressing element has a pressing part and a first actuation part. The pressing part has a through-hole. The pressing part moves relative to the first electronic element in a pressing direction. The pressing part drives the first actuation part to move when the pressing part moves so that the first actuation part actuates the first electronic element. The operation element has a driven part and a second actuation part. The second actuation part actuates the second electronic element. The driven part moves relative to the pressing part in an operation direction. The driven part drives the second actuation part to move when the driven part moves so that the second actuation part actuates the second electronic element. A projection device with the button module is also provided.

Abstract: The present invention provides a spin-orbit torque magnetic random access memory (SOT-MRAM) circuit, including a read transistor pair with two read transistors in parallel, a write transistor pair with two write transistors in parallel, a SOT memory cell with a magnetic tunnel junction (MTJ) and a SOT layer, wherein one end of the MTJ is connected to the source of the read transistor pair and the other end of the MTJ is connected to the SOT layer, and one end of the SOT layer is connected to a source line and the other of the SOT layer is connected to the source of the write transistor pair, a read bit line is connected to the drain of the read transistor pair and a write bit line is connected to the drain of the read transistor.

Abstract: An electronic device includes a first substrate, a second substrate, organic light emitting diodes, a filter layer, a third substrate, a structure, and a first adhesive element. At least a part of the organic light emitting diodes are disposed on the first substrate. The filter layer is disposed at least on the second substrate. The third substrate is disposed corresponding to the first substrate and the second substrate. The organic light emitting diodes and the structure are disposed under the third substrate. The first adhesive element is disposed between the first substrate and the second substrate, directly contacts the structure, and does not overlap with the organic light emitting diodes. A distance between a bottom surface of the structure and a top surface of the third substrate is different from a minimum distance between one of the organic light emitting diodes and the top surface of the third substrate.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a fin-shaped structure on a substrate, forming a gate material layer on the fin-shaped structure, performing an etching process to pattern the gate material layer for forming a gate structure and a silicon residue, performing an ashing process on the silicon residue, and then performing a cleaning process to transform the silicon residue into a polymer stop layer on a top surface and sidewalls of the fin-shaped structure.

Abstract: A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, an inter-metal dielectric (IMD) layer on the substrate, a MTJ in the IMD layer on the MTJ region, a first metal interconnection in the IMD layer on the logic region, and protrusions adjacent to two sides of the first metal interconnection. Preferably, the MTJ further includes a bottom electrode, a fixed layer, a barrier layer, a free layer, and a top electrode.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a first NMOS region, a first PMOS region, a second NMOS region, a second PMOS region, and a MOS capacitor region, forming a fin NMOS transistor on the first NMOS region, forming a fin PMOS transistor on the first PMOS region, forming a planar NMOS transistor on the second NMOS region, forming a planar PMOS transistor on the second PMOS region, and forming a planar MOS capacitor on the MOS capacitor region.

Abstract: A laptop computer is provided, including a main body and a display unit pivotally connected to each other. When the display unit is unfolded relative to the main body, a gear set inside the display unit rotates and drives a frame to move via a rack structure. Thus, the frame and a stylus pen in the frame move out of an opening in the front cover of the display unit so that the user can take out the stylus pen easily.

Abstract: A method of fabricating a contact structure includes the following steps. An opening is formed in a dielectric layer. A conductive material layer is formed within the opening and on the dielectric layer, wherein the conductive material layer includes a bottom section having a first thickness and a top section having a second thickness, the second thickness is greater than the first thickness. A first treatment is performed on the conductive material layer to form a first oxide layer on the bottom section and on the top section of the conductive material layer. A second treatment is performed to remove at least portions of the first oxide layer and at least portions of the conductive material layer, wherein after performing the second treatment, the bottom section and the top section of the conductive material layer have substantially equal thickness.

Abstract: A semiconductor device is disclosed. The device includes a source/drain feature formed over a substrate. A dielectric layer formed over the source/drain feature. A contact trench formed through the dielectric layer to expose the source/drain feature. A titanium nitride (TiN) layer deposited in the contact trench and a cobalt layer deposited over the TiN layer in the contact trench.

Abstract: A one-time programmable memory structure includes semiconductor substrate of a first conductivity type and a fin disposed on the semiconductor substrate. The fin extends along a first direction, wherein the fin includes a first portion and a second portion that is contiguous with the first portion. The first portion and the second portion have different cross-sectional profiles. A gate extends on the fin along a second direction. The gate partially overlaps the first portion of the fin and partially overlaps the second portion of the fin.

Abstract: A nanowire transistor includes a channel structure on a substrate, a gate structure on and around the channel structure, a source/drain structure adjacent to two sides of the gate structure, and a contact plug connected to the source/drain structure. Preferably, the source/drain structure includes graphene and the contact plug further includes a silicide layer on the source/drain structure, a graphene layer on the silicide layer, and a barrier layer on the graphene layer.

Abstract: An inspection system and an inspection method of a bare circuit board are provided. The inspection system is used for inspecting a bare circuit board. The bare circuit board includes a chip pad and an antenna. The inspection system includes an adapter board, a test device and a measure device. The adapter board includes a chip and a contact structure. The chip is electrically connected to the contact structure. The contact structure touches the chip pad so that the chip is electrically connected to the chip pad. The test device includes a transceiver antenna. The test device and the bare circuit board separate. The measure device is electrically connected to the chip or the transceiver antenna.

Abstract: A semiconductor device includes a substrate having a medium-voltage (MV) region and an one time programmable (OTP) capacitor region, a MV device on the MV region, and an OTP capacitor on the OTP capacitor region. Preferably, the MV device includes a first gate dielectric layer on the substrate, a first gate electrode on the first gate dielectric layer, and a shallow trench isolation (STI) adjacent to two sides of the first gate electrode. The OTP capacitor includes a fin-shaped structure on the substrate, a doped region in the fin-shaped structure, a second gate dielectric layer on the doped region, and a second gate electrode on the second gate dielectric layer.