Patents by Inventor Chun-Hsing Chen
Chun-Hsing Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11994534Abstract: A testing device for testing an integrated circuit package is provided, including a printed circuit board, a testing socket, a conductive fastener, a cover, and a conductive element assembly. The printed circuit board includes a first metal layer formed on the bottom surface thereof. The testing socket is disposed above the printed circuit board. The conductive fastener is configured to secure the testing socket to the printed circuit board, wherein the conductive fastener is electrically connected to the first metal layer and the testing socket. The cover is disposed above the testing socket to form a space for accommodating the integrated circuit package between the cover and the testing socket, wherein the cover makes electrical contact with the integrated circuit package. The conductive element assembly is disposed between and electrically connected to the cover and the testing socket.Type: GrantFiled: March 13, 2023Date of Patent: May 28, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shao-Chun Chiu, Wen-Feng Liao, Hao Chen, Chun-Hsing Chen
-
Publication number: 20230228793Abstract: A testing device for testing an integrated circuit package is provided, including a printed circuit board, a testing socket, a conductive fastener, a cover, and a conductive element assembly. The printed circuit board includes a first metal layer formed on the bottom surface thereof. The testing socket is disposed above the printed circuit board. The conductive fastener is configured to secure the testing socket to the printed circuit board, wherein the conductive fastener is electrically connected to the first metal layer and the testing socket. The cover is disposed above the testing socket to form a space for accommodating the integrated circuit package between the cover and the testing socket, wherein the cover makes electrical contact with the integrated circuit package. The conductive element assembly is disposed between and electrically connected to the cover and the testing socket.Type: ApplicationFiled: March 13, 2023Publication date: July 20, 2023Inventors: Shao-Chun CHIU, Wen-Feng LIAO, Hao CHEN, Chun-Hsing CHEN
-
Patent number: 11604211Abstract: A testing device for testing an integrated circuit package is provided, including a printed circuit board having a first surface, a second surface, and multiple conductive layers between the first and second surfaces. A metal layer is formed on the second surface and is electrically connected to one of the conductive layers that is grounded. A testing socket is disposed over the first surface. A conductive fastener secures the testing socket to the printed circuit board and is electrically connected to the metal layer. A cover is disposed over the testing socket to form a space for accommodating the integrated circuit package between the cover and the testing socket. The cover has a conductive surface in contact with the integrated circuit package. A conductive element assembly is disposed between the cover and the testing socket and is electrically connected to the conductive surface and the conductive fastener.Type: GrantFiled: August 30, 2021Date of Patent: March 14, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shao-Chun Chiu, Wen-Feng Liao, Hao Chen, Chun-Hsing Chen
-
Publication number: 20230063518Abstract: A testing device for testing an integrated circuit package is provided, including a printed circuit board having a first surface, a second surface, and multiple conductive layers between the first and second surfaces. A metal layer is formed on the second surface and is electrically connected to one of the conductive layers that is grounded. A testing socket is disposed over the first surface. A conductive fastener secures the testing socket to the printed circuit board and is electrically connected to the metal layer. A cover is disposed over the testing socket to form a space for accommodating the integrated circuit package between the cover and the testing socket. The cover has a conductive surface in contact with the integrated circuit package. A conductive element assembly is disposed between the cover and the testing socket and is electrically connected to the conductive surface and the conductive fastener.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Inventors: Shao-Chun CHIU, Wen-Feng LIAO, Hao CHEN, Chun-Hsing CHEN
-
Publication number: 20150175448Abstract: A system for treating wastewater containing boron and iodine is provided. The system comprises a membrane filter, an electrodeionization filter and a resin adsorption column. The membrane filter is provided for removing iodine from the wastewater. The electrodeionization filter is connected to the membrane filter via lines for removing boron from the wastewater. The resin adsorption column is connected to the electrodeionization filter via lines for removing the residual boron from the wastewater. The boron and iodine can be removed efficiently to meet the wastewater discharging standard by using the system for treating wastewater containing boron and iodine.Type: ApplicationFiled: August 15, 2014Publication date: June 25, 2015Inventors: Cheng-Lin CHUNG, Chun-Hsing CHEN, Chyi-Ching LIN
-
Patent number: 8146245Abstract: A method for assembling a probe card for wafer level testing of a plurality of semiconductor devices simultaneously is disclosed. The probe card may include a circuit board including wafer level testing circuitry, a partially flexible silicon substrate, a plurality of test probes disposed at least partially in the substrate for engaging a plurality of corresponding electrical contacts in a wafer under test, and a compressible underfill coupling the substrate to the circuit board. The method includes aligning and assembling the foregoing components, and curing the underfill. The probe card may be used for wafer level burn-in testing. In some embodiments, the probe card may include active test control circuitry embedded in the silicon substrate for conducting wafer level high frequency testing.Type: GrantFiled: May 26, 2010Date of Patent: April 3, 2012Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.Inventors: Clinton Chih-Chieh Chao, Fei-Chieh Yang, Chun-Hsing Chen, Mill-Jer Wang, Sheng-Hsi Huang, Ming-Cheng Hsu
-
Publication number: 20100229383Abstract: A probe card for wafer level testing of a plurality of semiconductor devices simultaneously. The probe card may include a circuit board including wafer level testing circuitry, a partially flexible silicon substrate, a plurality of test probes disposed at least partially in the substrate for engaging a plurality of corresponding electrical contacts in a wafer under test, and a compressible underfill coupling the substrate to the circuit board. The probe card may be used for wafer level burn-in testing. In some embodiments, the probe card may include active test control circuitry embedded in the silicon substrate for conducting wafer level high frequency testing.Type: ApplicationFiled: May 26, 2010Publication date: September 16, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Clinton Chih-Chieh Chao, Fei-Chieh Yang, Chun-Hsing Chen, Mill-Jer Wang, Sheng-Hsi Huang, Ming-Cheng Hsu
-
Patent number: 7750651Abstract: A probe card for wafer level testing of a plurality of semiconductor devices simultaneously. The probe card may include a circuit board including wafer level testing circuitry, a partially flexible silicon substrate, a plurality of test probes disposed at least partially in the substrate for engaging a plurality of corresponding electrical contacts in a wafer under test, and a compressible underfill coupling the substrate to the circuit board. The probe card may be used for wafer level burn-in testing. In some embodiments, the probe card may include active test control circuitry embedded in the silicon substrate for conducting wafer level high frequency testing.Type: GrantFiled: June 3, 2008Date of Patent: July 6, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Clinton Chih-Chieh Chao, Fei-Chieh Yang, Chun-Hsing Chen, Mill-Jer Wang, Sheng-Hsi Huang, Ming-Cheng Hsu
-
Publication number: 20090224780Abstract: A probe card for wafer level testing of a plurality of semiconductor devices simultaneously. The probe card may include a circuit board including wafer level testing circuitry, a partially flexible silicon substrate, a plurality of test probes disposed at least partially in the substrate for engaging a plurality of corresponding electrical contacts in a wafer under test, and a compressible underfill coupling the substrate to the circuit board. The probe card may be used for wafer level burn-in testing. In some embodiments, the probe card may include active test control circuitry embedded in the silicon substrate for conducting wafer level high frequency testing.Type: ApplicationFiled: June 3, 2008Publication date: September 10, 2009Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Clinton Chih-Chieh Chao, Fei-Chieh Yang, Chun-Hsing Chen, Mill-Jer Wang, Sheng-Hsi Huang, Ming-Cheng Hsu