Patents by Inventor Chun-Hsiung Tsai

Chun-Hsiung Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190252201
    Abstract: Semiconductor devices and methods for manufacturing the same are disclosed. In an embodiment, a method of manufacturing a semiconductor device may include providing a substrate having a recess; epitaxially forming a first layer including a doped semiconductor material within the recess; and epitaxially forming a second layer including an undoped semiconductor material over at least a portion of the recess.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 15, 2019
    Inventors: Chun Hsiung Tsai, Tsz-Mei Kwok
  • Publication number: 20190245087
    Abstract: The present disclosure provides a semiconductor device structure in accordance with some embodiments. In some embodiments, the semiconductor device structure includes a semiconductor substrate of a first semiconductor material and having first recesses. The semiconductor device structure further includes a first gate stack formed on the semiconductor substrate and being adjacent the first recesses. In some examples, a passivation material layer of a second semiconductor material is formed in the first recesses. In some embodiments, first source and drain (S/D) features of a third semiconductor material are formed in the first recesses and are separated from the semiconductor substrate by the passivation material layer. In some cases, the passivation material layer is free of chlorine.
    Type: Application
    Filed: April 15, 2019
    Publication date: August 8, 2019
    Inventors: Chun Hsiung TSAI, Yuan-Ko HWANG
  • Publication number: 20190237543
    Abstract: A method includes providing a structure having a substrate, a fin, and a gate structure; performing an implantation process to implant a dopant into the fin adjacent to the gate structure; and forming gate sidewall spacers and fin sidewall spacers. The method further includes performing a first etching process to recess the fin adjacent to the gate sidewall spacers while keeping at least a portion of the fin above the fin sidewall spacers. The method further includes performing another implantation process to implant the dopant into the fin and the fin sidewall spacers; and performing a second etching process to recess the fin adjacent to the gate sidewall spacers until a top surface of the fin is below a top surface of the fin sidewall spacers, resulting in a trench between the fin sidewall spacers. The method further includes epitaxially growing a semiconductor material in the trench.
    Type: Application
    Filed: January 29, 2018
    Publication date: August 1, 2019
    Inventors: Chun Hsiung Tsai, Ya-Yun Cheng, Shahaji B. More, Cheng-Yi Peng, Wei-Yang Lee, Kuo-Feng Yu, Yen-Ming Chen, Jian-Hao Chen
  • Patent number: 10367308
    Abstract: An electrical connector includes an insulative housing defining a front cavity for receiving and rear cavity, a terminal assembly assembled in the rear cavity, and a ground member. The terminal assembly includes an upper terminal module, a lower terminal module sandwiching a shielding module therebetween. Said upper terminal module includes a pair of upper ground terminals. Said lower terminal module includes a plurality of lower ground terminals. Said shielding module includes metallic shielding plate. The ground member is associated with the shielding module to mechanically and electrically connect at least one of the upper ground terminals and the lower ground terminals with the shielding plate.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: July 30, 2019
    Assignee: FOXCONN INTERCONNECT TECHNOLOGY LIMITED
    Inventors: Terrance F. Little, Chih-Hsien Chou, Chun-Hsiung Hsu, Kuei-Chung Tsai
  • Patent number: 10361279
    Abstract: Methods for forming semiconductor structures are provided. The method includes forming a fin structure over a substrate and forming a gate structure across the fin structure. The method further includes forming a fin spacer on a sidewall of the fin structure and partially removing the fin spacer. The method further includes recessing the fin structure to form a recess and implanting dopants from the recess to form a doped region. The method further includes diffusing the dopants in the doped region to form an expanded doped region and forming a source/drain structure over the expanded doped region.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: July 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shahaji B. More, Chun-Hsiung Tsai, Cheng-Yi Peng, Shih-Chieh Chang, Kuo-Feng Yu
  • Patent number: 10340269
    Abstract: An embodiment is a method of manufacturing a semiconductor device, the method including forming a first gate over a substrate, forming a recess in the substrate adjacent the first gate, epitaxially forming a strained material stack in the recess, the strained material stack comprising at least three layers, each of the at least three layers comprising a dopant. The method further includes co-implanting the strained material stack with dopants comprising boron, germanium, indium, tin, or a combination thereof, forming a metal layer on the strained material stack, and annealing the metal layer and the strained material stack forming a metal-silicide layer.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: July 2, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Ming-Te Chen
  • Publication number: 20190165124
    Abstract: A semiconductor structure includes a substrate, a semiconductor fin connected to the substrate, an epitaxial layer disposed over the semiconductor fin, and a silicide feature over and in contact with the epitaxial layer. The epitaxial layer including silicon germanium (SiGe) and further includes gallium (Ga) in an upper portion of the epitaxial layer that is in contact with the silicide feature.
    Type: Application
    Filed: December 6, 2018
    Publication date: May 30, 2019
    Inventors: Shahaji B. More, Chun Hsiung Tsai, Shih-Chieh Chang, Kuo-Feng Yu, Cheng-Yi Peng
  • Publication number: 20190165174
    Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a channel region and a source/drain region disposed adjacent to the channel region. The FET also includes a gate electrode disposed over the channel region. The FET is an n-type FET and the channel region is made of Si. The source/drain region includes an epitaxial layer including Si1-x-yM1xM2y, where M1 is one or more of Ge and Sn, and M2 is one or more of P and As, and 0.01?x?0.1.
    Type: Application
    Filed: February 28, 2018
    Publication date: May 30, 2019
    Inventors: Cheng-Yi PENG, Carlos H. DIAZ, Chun Hsiung TSAI, Yu-Ming LIN
  • Publication number: 20190165518
    Abstract: An electrical connector (100) includes an insulative housing (1), and a number of contacts received therein. The contacts include a pair of first and second grounding contacts (212, 222), and a pair of first and second signal contacts (211, 221). Each of the first signal and grounding contacts includes a first contact portion (213), a first mounting portion (214), a first horizontal portion (215), and a first connecting portion (216). Each of the second signal and grounding contacts includes a second contact portion (223), a second mounting portion (224), and a second horizontal portion (225). A first distance (d1) between the first connecting portion and the second mounting portion is greater than a second distance (d2) between the first and second horizontal portions, and is also greater than a third distance (d3) between the first and second mounting portions.
    Type: Application
    Filed: October 26, 2018
    Publication date: May 30, 2019
    Inventors: CHUN-HSIUNG HSU, KUEI-CHUNG TSAI
  • Publication number: 20190165143
    Abstract: Methods for forming semiconductor structures are provided. The method includes forming a fin structure over a substrate and forming a gate structure across the fin structure. The method further includes forming a fin spacer on a sidewall of the fin structure and partially removing the fin spacer. The method further includes recessing the fin structure to form a recess and implanting dopants from the recess to form a doped region. The method further includes diffusing the dopants in the doped region to form an expanded doped region and forming a source/drain structure over the expanded doped region.
    Type: Application
    Filed: May 31, 2018
    Publication date: May 30, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shahaji B. MORE, Chun-Hsiung TSAI, Cheng-Yi PENG, Shih-Chieh CHANG, Kuo-Feng YU
  • Publication number: 20190155983
    Abstract: The present disclosure describes a method for detecting unacceptable connection patterns. The method includes, using a processor to perform at least one of: performing an automated place-and-route (APR) process on a circuit layout that includes a first standard cell without a marker layer to generate a circuit graphic database system (GDS) file from the circuit layout, generating a standard-cell GDS file that includes a second standard cell with at least one marker layer applied to the second standard cell, and merging the circuit GDS file with the standard-cell GDS file to generate a merged GDS file that includes the first standard cell with at least one marker layer based on the second standard cell. The method further includes determining whether a connection pattern of the first standard cell in the merged GDS file is an unacceptable connection pattern.
    Type: Application
    Filed: February 28, 2018
    Publication date: May 23, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Hsiung CHEN, Ming-Huei Tsai, Shao-Huan Wang, Shu-Yu Chen, Wen-Hao Chen, Chun-Chen Chen
  • Patent number: 10297492
    Abstract: The embodiments of mechanisms for doping wells of finFET devices described in this disclosure utilize depositing doped films to dope well regions. The mechanisms enable maintaining low dopant concentration in the channel regions next to the doped well regions. As a result, transistor performance can be greatly improved. The mechanisms involve depositing doped films prior to forming isolation structures for transistors. The dopants in the doped films are used to dope the well regions near fins. The isolation structures are filled with a flowable dielectric material, which is converted to silicon oxide with the usage of microwave anneal. The microwave anneal enables conversion of the flowable dielectric material to silicon oxide without causing dopant diffusion. Additional well implants may be performed to form deep wells. Microwave anneal(s) may be used to anneal defects in the substrate and fins.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: May 21, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chun Hsiung Tsai, Yan-Ting Lin, Clement Hsingjen Wann
  • Publication number: 20190140089
    Abstract: A method includes forming a first channel region and a first gate structure formed over the first channel region. A first source/drain region is formed adjacent the first channel region and the first source/drain region includes a crystalline structure doped with a first dopant. A first silicide is formed over the first source/drain region. The first source/drain region includes a first concentration of the first dopant between 2.0×1021 atoms per centimeter cubed and 4.0×1021 atoms per centimeter cubed at a depth of 8 to 10 nanometers.
    Type: Application
    Filed: December 17, 2018
    Publication date: May 9, 2019
    Inventors: Chun Hsiung Tsai, Sheng-Wen Yu, Ziwei Fang
  • Patent number: 10276715
    Abstract: A fin field effect transistor (FinFET) is provided. The FinFET includes a substrate, a gate stack, and strained source and drain regions. The substrate has a semiconductor fin. The gate stack is disposed across the semiconductor fin. Moreover, the strained source and drain regions are located within recesses of the semiconductor fin beside the gate stack. Moreover, at least one of the strained source and drain regions has a top portion and a bottom portion, the bottom portion is connected to the top portion, and a bottom width of the top portion is greater than a top width of the bottom portion.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun Hsiung Tsai, Chien-Tai Chan, Kuo-Feng Yu, Kei-Wei Chen
  • Patent number: 10269577
    Abstract: Semiconductor devices and methods for manufacturing the same are disclosed. In an embodiment, a method of manufacturing a semiconductor device may include providing a substrate having a recess; epitaxially forming a first layer including a doped semiconductor material within the recess; and epitaxially forming a second layer including an undoped semiconductor material over at least a portion of the recess.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Tsz-Mei Kwok
  • Publication number: 20190115428
    Abstract: Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and removing the dielectric material in the isolation structures neighboring fins to increase epitaxial regions for dislocation formation. The mechanisms also involve performing a pre-amorphous implantation (PAI) process either before or after the epitaxial growth in the recessed source and drain regions. An anneal process after the PAI process enables consistent growth of the dislocations in the source and drain regions. The dislocations in the source and drain regions (or stressor regions) can form consistently to produce targeted strain in the source and drain regions to improve carrier mobility and device performance for NMOS devices.
    Type: Application
    Filed: December 5, 2018
    Publication date: April 18, 2019
    Inventors: Chun Hsiung Tsai, Wei-Yuan Lu, Chien-Tai Chan, Wei-Yang Lee, Da-Wen Lin
  • Patent number: 10263108
    Abstract: The present disclosure provides a method forming a field effect transistor (FET) in accordance with some embodiments. The method includes performing an etching process to a semiconductor substrate, thereby forming recesses in source and drain (S/D) regions of the semiconductor substrate; forming a passivation material layer of a first semiconductor in the recesses; and epitaxially growing a second semiconductor material, thereby forming S/D features in the recesses, wherein the S/D features are separated from the semiconductor substrate by the passivation material layer.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: April 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Yuan-Ko Hwang
  • Publication number: 20190109213
    Abstract: A structure includes a semiconductor substrate, a source epitaxial structure, a drain epitaxial structure, and a gate stack. The source epitaxial structure is in the semiconductor substrate. The source epitaxial structure has a top surface, and the top surface of the source epitaxial structure comprises hydrogen. The drain epitaxial structure is in the semiconductor substrate. The gate stack is over the semiconductor substrate and between the source epitaxial structure and the drain epitaxial structure.
    Type: Application
    Filed: November 27, 2018
    Publication date: April 11, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Hsiung TSAI, Kei-Wei CHEN
  • Publication number: 20190097051
    Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure extended above a substrate and a gate structure formed over a middle portion of the fin structure. The middle portion of the fin structure is wrapped by the gate structure. The FinFET device structure includes a source/drain (S/D) structure adjacent to the gate structure, and the S/D structure includes a doped region at an outer portion of the S/D structure, and the doped region includes gallium (Ga). The FinFET device structure includes a metal silicide layer formed over the doped region of the S/D structure, and the metal silicide layer is in direct contact with the doped region of the S/D structure.
    Type: Application
    Filed: February 9, 2018
    Publication date: March 28, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Hsiung TSAI, Shahaji B. MORE, Cheng-Yi PENG, Yu-Ming LIN, Kuo-Feng YU, Ziwei FANG
  • Publication number: 20190027579
    Abstract: A fin-type field effect transistor including a substrate, insulators, a gate stack, a first spacer, a second spacer, and a third spacer is described. The substrate has fins thereon. The insulators are located over the substrate and between the fins. The gate stack is located over the fins and over the insulators. The first spacer is located over the sidewall of the gate stack. The second spacer is located over the first spacer. The first spacer and the second spacer includes carbon. The third spacer is located between the first spacer and the second spacer.
    Type: Application
    Filed: September 16, 2018
    Publication date: January 24, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Hsiung Tsai, Kei-Wei Chen