Patents by Inventor Chun-Hsiung Tsai

Chun-Hsiung Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210328016
    Abstract: The present disclosure provides an LDD-free semiconductor structure including a semiconductor layer, a gate over the semiconductor layer and a regrowth region made of semiconductor material positioned in the semiconductor layer. The regrowth region forms a source region or a drain region of the LDD-free semiconductor structure. The gate includes a gate electrode layer laterally covered by a gate spacer. The regrowth region extends towards a region beneath the gate spacer and close to a plane extending along a junction of the gate spacer and the gate electrode layer. The present disclosure also provides a method for manufacturing an LDD-free semiconductor structure. The method includes forming a gate over a semiconductor layer, removing a portion of the semiconductor layer and obtaining a recess, and forming a regrowth region over the recess.
    Type: Application
    Filed: June 30, 2021
    Publication date: October 21, 2021
    Inventor: CHUN HSIUNG TSAI
  • Publication number: 20210320448
    Abstract: An electrical connector includes an insulating body, a first terminal group having a signal terminal pair and a ground terminal arranged on one side of the signal terminal pair, each signal terminal having a tail portion, a contact portion, and a body portion, the body portion having a covering portion and a free portion exposed to air, wherein there is a first center distance between the contact portions of the signal terminal pair, there is a second center distance between the free portions, and there is a third center distance between the covering parts, and a second terminal group forming a first mating port with the first terminal group, wherein the second center distance is smaller than the first center distance, and the third center distance is greater than the second center distance.
    Type: Application
    Filed: April 6, 2021
    Publication date: October 14, 2021
    Inventors: CHIH-PING CHUNG, KUEI-CHUNG TSAI, CHUN-HSIUNG HSU
  • Patent number: 11133222
    Abstract: Methods of manufacturing a semiconductor structure are provided. One of the methods includes the following operations. A substrate is received, and the substrate includes a first transistor with a first conductive region and a second transistor with a second conductive region, wherein the first transistor and the second transistor have different conductive types. A first laser anneal is performed on the first conductive region to repair lattice damage. An amorphization is performed on the first conductive region and the second conductive region to enhance silicide formation to a desired phase transformation in the subsequent operations. A pre-silicide layer is formed on the substrate after the amorphization. A thermal anneal is performed to the substrate to form a silicide layer from the pre-silicide layer. A second laser anneal is performed on the first conductive region and the second conductive region after the formation of the pre-silicide layer.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: September 28, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun Hsiung Tsai, Cheng-Yi Peng, Ching-Hua Lee, Clement Hsingjen Wann, Yu-Ming Lin
  • Publication number: 20210288146
    Abstract: Present disclosure provides a FinFET structure, including a substrate, a fin protruding from the substrate, including a first portion and a second portion below the first portion, wherein the first portion includes a first dopant concentration of a dopant, and the second portion includes a second dopant concentration of the dopant, the second dopant concentration is greater than the first dopant concentration, a gate over the fin, wherein the second portion of the fin is below a bottom surface of the gate, and an insulating layer over the substrate and proximal to the second portion of the fin, wherein at least a first portion of the insulating layer includes a third dopant concentration of the dopant, the third dopant concentration is greater than the first dopant concentration.
    Type: Application
    Filed: June 1, 2021
    Publication date: September 16, 2021
    Inventors: CHUN HSIUNG TSAI, LAI-WAN CHONG, CHIEN-WEI LEE, KEI-WEI CHEN
  • Patent number: 11121168
    Abstract: A back side illumination (BSI) image sensor with a dielectric grid opening having a planar lower surface is provided. A pixel sensor is arranged within a semiconductor substrate. A metallic grid is arranged over the pixel sensor and defines a sidewall of a metallic grid opening. A dielectric grid is arranged over the metallic grid and defines a sidewall of the dielectric grid opening. A capping layer is arranged over the metallic grid, and defines the planar lower surface of the dielectric grid opening.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun-Wei Cheng, Horng Huei Tseng, Chao-Hsiung Wang, Chun-Hao Chou, Tsung-Han Tsai, Kuo-Cheng Lee, Tzu-Hsuan Hsu, Yung-Lung Hsu
  • Publication number: 20210273099
    Abstract: In a method of manufacturing a semiconductor device, an upper fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed over a lower fin structure, a sacrificial gate structure is formed over the upper fin structure, a source/drain region of the upper fin structure, which is not covered by the sacrificial gate structure, is etched thereby forming a source/drain space, the first semiconductor layers are laterally etched through the source/drain space, an inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers, and a source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. In etching the source/drain region, a part of the lower fin structure is also etched to form a recess, in which a (111) surface is exposed.
    Type: Application
    Filed: July 20, 2020
    Publication date: September 2, 2021
    Inventors: Shahaji B. MORE, Chun Hsiung TSAI
  • Publication number: 20210257493
    Abstract: A semiconductor Fin FET device includes a fin structure disposed over a substrate. The fin structure includes a channel layer. The Fin FET device also includes a gate structure including a gate electrode layer and a gate dielectric layer, covering a portion of the fin structure. Side-wall insulating layers are disposed over both main sides of the gate electrode layer. The Fin FET device includes a source and a drain, each including a stressor layer disposed in a recess formed by removing the fin structure not covered by the gate structure. The stressor layer includes a first to a third stressor layer formed in this order. In the source, an interface between the first stressor layer and the channel layer is located under one of the side-wall insulating layers closer to the source or the gate electrode.
    Type: Application
    Filed: March 1, 2021
    Publication date: August 19, 2021
    Inventors: Chun Hsiung TSAI, Kei-Wei CHEN
  • Patent number: 11094797
    Abstract: A structure includes a semiconductor substrate, a source epitaxial structure, a drain epitaxial structure, and a gate stack. The source epitaxial structure is in the semiconductor substrate. The source epitaxial structure has a top surface, and the top surface of the source epitaxial structure comprises hydrogen. The drain epitaxial structure is in the semiconductor substrate. The gate stack is over the semiconductor substrate and between the source epitaxial structure and the drain epitaxial structure.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: August 17, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Hsiung Tsai, Kei-Wei Chen
  • Patent number: 11088248
    Abstract: The present disclosure provides an LDD-free semiconductor structure including a semiconductor layer, a gate over the semiconductor layer and a regrowth region made of semiconductor material positioned in the semiconductor layer. The regrowth region forms a source region or a drain region of the LDD-free semiconductor structure. The gate includes a gate electrode layer laterally covered by a gate spacer. The regrowth region extends towards a region beneath the gate spacer and close to a plane extending along a junction of the gate spacer and the gate electrode layer. The present disclosure also provides a method for manufacturing an LDD-free semiconductor structure. The method includes forming a gate over a semiconductor layer, removing a portion of the semiconductor layer and obtaining a recess, and forming a regrowth region over the recess.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: August 10, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Chun Hsiung Tsai
  • Publication number: 20210242310
    Abstract: A semiconductor device includes a substrate; an isolation structure over the substrate; a fin over the substrate and the isolation structure; a gate structure engaging a first portion of the fin; first sidewall spacers over sidewalls of the gate structure and over a second portion of the fin; source/drain (S/D) features adjacent to the first sidewall spacers; and second sidewall spacers over the isolation structure and over sidewalls of a portion of the S/D features. The second sidewall spacers include silicon oxide, silicon nitride, or silicon oxynitride. The second sidewall spacers and the second portion of the fin include a same dopant, wherein the dopant includes phosphorus.
    Type: Application
    Filed: April 26, 2021
    Publication date: August 5, 2021
    Inventors: Chun Hsiung Tsai, Ya-Yun Cheng, Shahaji B. More, Cheng-Yi Peng, Wei-Yang Lee, Kuo-Feng Yu, Yen-Ming Chen, Jian-Hao Chen
  • Patent number: 11075108
    Abstract: The embodiments of mechanisms for doping wells of finFET devices described in this disclosure utilize depositing doped films to dope well regions. The mechanisms enable maintaining low dopant concentration in the channel regions next to the doped well regions. As a result, transistor performance can be greatly improved. The mechanisms involve depositing doped films prior to forming isolation structures for transistors. The dopants in the doped films are used to dope the well regions near fins. The isolation structures are filled with a flowable dielectric material, which is converted to silicon oxide with the usage of microwave anneal. The microwave anneal enables conversion of the flowable dielectric material to silicon oxide without causing dopant diffusion. Additional well implants may be performed to form deep wells. Microwave anneal(s) may be used to anneal defects in the substrate and fins.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chun Hsiung Tsai, Yan-Ting Lin, Clement Hsingjen Wann
  • Publication number: 20210202718
    Abstract: A fin-type field effect transistor including a substrate, insulators, a gate stack, a first spacer, a second spacer, and a third spacer is described. The substrate has fins thereon. The insulators are located over the substrate and between the fins. The gate stack is located over the fins and over the insulators. The first spacer is located over the sidewall of the gate stack. The second spacer is located over the first spacer. The first spacer and the second spacer includes carbon. The third spacer is located between the first spacer and the second spacer.
    Type: Application
    Filed: March 15, 2021
    Publication date: July 1, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Kei-Wei Chen
  • Patent number: 10991800
    Abstract: A semiconductor device includes a substrate, an isolation structure over the substrate, a fin over the substrate and the isolation structure, a gate structure engaging a first portion of the fin, first sidewall spacers over sidewalls of the gate structure and over a second portion of the fin, source/drain (S/D) features adjacent to the first sidewall spacers, and second sidewall spacers over the isolation structure and over sidewalls of a portion of the S/D features. The second sidewall spacers and the second portion of the fin include a same dopant.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: April 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun Hsiung Tsai, Ya-Yun Cheng, Shahaji B. More, Cheng-Yi Peng, Wei-Yang Lee, Kuo-Feng Yu, Yen-Ming Chen, Jian-Hao Chen
  • Publication number: 20210104619
    Abstract: A method for forming a semiconductor structure is provided. The method includes the following operations. A substrate is received. A fin structure is formed on the substrate, and a dielectric layer is formed over the fin structure. A sacrificial gate is formed over the substrate. A portion of the dielectric layer is exposed through the sacrificial gate. Recesses are formed in the fin structure at two sides of the sacrificial gate. A cleaning operation is performed with an HF-containing plasma. The HF-containing plasma includes HF and NH3.
    Type: Application
    Filed: November 23, 2020
    Publication date: April 8, 2021
    Inventors: CHUN HSIUNG TSAI, RU-SHANG HSIAO, CLEMENT HSINGJEN WANN
  • Publication number: 20210082706
    Abstract: A method includes forming a first gate dielectric and a second gate dielectric over a first semiconductor region and a second semiconductor region, respectively, depositing a lanthanum-containing layer including a first portion and a second portion overlapping the first gate dielectric and the second gate dielectric, respectively, and depositing a hard mask including a first portion and a second portion overlapping the first portion and the second portion of the lanthanum-containing layer, respectively. The hard mask is free from both of titanium and tantalum. The method further includes forming a patterned etching mask to cover the first portion of the hard mask, with the second portion of the hard mask being exposed, removing the second portion of the hard mask and the second portion of the lanthanum-containing layer, and performing an anneal to drive lanthanum in the first portion of the lanthanum-containing layer into the first gate dielectric.
    Type: Application
    Filed: September 17, 2019
    Publication date: March 18, 2021
    Inventors: Kuo-Feng Yu, Chun Hsiung Tsai, Jian-Hao Chen, Hoong Shing Wong, Chih-Yu Hsu
  • Patent number: 10950710
    Abstract: A fin-type field effect transistor including a substrate, insulators, a gate stack, a first spacer, a second spacer, and a third spacer is described. The substrate has fins thereon. The insulators are located over the substrate and between the fins. The gate stack is located over the fins and over the insulators. The first spacer is located over the sidewall of the gate stack. The second spacer is located over the first spacer. The first spacer and the second spacer includes carbon. The third spacer is located between the first spacer and the second spacer.
    Type: Grant
    Filed: September 16, 2018
    Date of Patent: March 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hsiung Tsai, Kei-Wei Chen
  • Publication number: 20210074590
    Abstract: A semiconductor device and a method of forming the same are provided. A method includes forming a sacrificial gate over an active region of a substrate. The sacrificial gate is removed to form an opening. A gate dielectric layer is formed on sidewalls and a bottom of the opening. A first work function layer is formed over the gate dielectric layer in the opening. A first protective layer is formed over the first work function layer in the opening. A first etch process is performed to widen an upper portion of the opening. The opening is filled with a conductive material.
    Type: Application
    Filed: September 9, 2019
    Publication date: March 11, 2021
    Inventors: Shahaji B. More, Chandrashekhar Prakash Savant, Chun Hsiung Tsai
  • Patent number: 10943790
    Abstract: Semiconductor devices and methods for manufacturing the same are disclosed. In an embodiment, a method of manufacturing a semiconductor device may include providing a substrate having a recess; epitaxially forming a first layer including a doped semiconductor material within the recess; and epitaxially forming a second layer including an undoped semiconductor material over at least a portion of the recess.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: March 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Tsz-Mei Kwok
  • Patent number: 10937906
    Abstract: A semiconductor Fin FET device includes a fin structure disposed over a substrate. The fin structure includes a channel layer. The Fin FET device also includes a gate structure including a gate electrode layer and a gate dielectric layer, covering a portion of the fin structure. Side-wall insulating layers are disposed over both main sides of the gate electrode layer. The Fin FET device includes a source and a drain, each including a stressor layer disposed in a recess formed by removing the fin structure not covered by the gate structure. The stressor layer includes a first to a third stressor layer formed in this order. In the source, an interface between the first stressor layer and the channel layer is located under one of the side-wall insulating layers closer to the source or the gate electrode.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: March 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun Hsiung Tsai, Kei-Wei Chen
  • Patent number: 10923595
    Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a channel region and a source/drain region disposed adjacent to the channel region. The FET also includes a gate electrode disposed over the channel region. The FET is an n-type FET and the channel region is made of Si. The source/drain region includes an epitaxial layer including Si1?x?yM1xM2y, where M1 is one or more of Ge and Sn, and M2 is one or more of P and As, and 0.01?x?0.1.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: February 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yi Peng, Carlos H. Diaz, Chun Hsiung Tsai, Yu-Ming Lin