Abstract: A latch assembly may include a guide base configured to fixedly couple to a circuit board and having a guiding feature, an axis configured to rotatably couple to the circuit board and having a driving feature, and a sliding latch including a guide feature configured to mechanically engage with the guiding feature to constrain movement of the sliding latch in a linear direction relative to the circuit board and a drive feature configured to mechanically engage with the driving feature such that in a first rotational position of the axis relative to the circuit board, the driving feature mechanically drives the sliding latch to a first position relative to a connector of the circuit board and in a second rotational position of the axis relative to the circuit board, the driving feature mechanically drives the sliding latch to a second position relative to the connector.

Abstract: A latch assembly may include a guide base configured to fixedly couple to a circuit board and having a guiding feature, an axis configured to rotatably couple to the circuit board and having a driving feature, and a sliding latch including a guide feature configured to mechanically engage with the guiding feature to constrain movement of the sliding latch in a linear direction relative to the circuit board and a drive feature configured to mechanically engage with the driving feature such that in a first rotational position of the axis relative to the circuit board, the driving feature mechanically drives the sliding latch to a first position relative to a connector of the circuit board and in a second rotational position of the axis relative to the circuit board, the driving feature mechanically drives the sliding latch to a second position relative to the connector.

Abstract: The present disclosure is related to a lead frame structure. The lead frame structure includes a bottom board and a blocking wall. The bottom board has a first conductive portion and a second conductive portion. The first conductive portion separates from the second conductive portion. The first and second conductive portions are configured to electrically connect to a light source. The blocking wall is located on the bottom board, and the blocking wall surrounds an opening. The first and the second conductive portions are exposed from the opening. The first and the second conductive portions each have an extending portion. The extending portion extends beyond an external surface of the blocking wall in a horizontal direction.

Abstract: The present disclosure is related to a lead frame structure. The lead frame structure includes a bottom board and a blocking wall. The bottom board has a first conductive portion and a second conductive portion. The first conductive portion separates from the second conductive portion. The first and second conductive portions are configured to electrically connect to a light source. The blocking wall is located on the bottom board, and the blocking wall surrounds an opening. The first and the second conductive portions are exposed from the opening. The first and the second conductive portions each have an extending portion. The extending portion extends beyond an external surface of the blocking wall in a horizontal direction.

Abstract: A semiconductor device includes: a gate structure extending along a first direction on a substrate, in which the gate structure includes a first edge and a second edge extending along the first direction; a first doped region adjacent to one side of the gate structure, in which the first doped region includes a third edge and a fourth edge extending along the first direction; a second doped region adjacent to another side of the gate structure, in which the second doped region comprises a fifth edge and a sixth edge extending along the first direction; a first fin-shaped structure extending from the second edge of the gate structure toward the third edge of the first doped region; and a second fin-shaped structure extending from the first edge of the gate structure toward the sixth edge of the second doped region.

Abstract: A light emitting device includes a transistor and the transistor has a gate layer, and a dielectric under the gate layer. The light emitting device also includes a capacitor coupled to the transistor The capacitor including a first electrode, a second electrode over the first electrode, and a dielectric between the first and second electrode. The tight emitting device further includes a contact dielectric seprataing the transistor and the capacitor. The dielectric fully surrounds the capacitor and the transistor, wherein the contact dielectric is nitrogen free.

Abstract: A semiconductor device includes: a gate structure extending along a first direction on a substrate, in which the gate structure includes a first edge and a second edge extending along the first direction; a first doped region adjacent to one side of the gate structure, in which the first doped region includes a third edge and a fourth edge extending along the first direction; a second doped region adjacent to another side of the gate structure, in which the second doped region comprises a fifth edge and a sixth edge extending along the first direction; a first fin-shaped structure extending from the second edge of the gate structure toward the third edge of the first doped region; and a second fin-shaped structure extending from the first edge of the gate structure toward the sixth edge of the second doped region.

Abstract: A semiconductor device includes: a gate structure on a substrate; a first doped region adjacent to one side of the gate structure; a second doped region adjacent to another side of the gate structure; and fin-shaped structures on the substrate. Preferably, a number of the fin-shaped structures covered by the gate structure is different from a number of the fin-shaped structures overlapping the first doped region or the second doped region.

Abstract: A power supply apparatus with reverse current protection includes a digital signal processor, a secondary side rectifying circuit, a voltage detection unit and a current detection unit. A plurality of the power supply apparatuses are connected in parallel and applied to a server system. When the voltage detection unit detects that a bus voltage is greater than a predetermined voltage and the current detection unit detects that an output current is less than a predetermined current, the voltage detection unit and the current detection unit inform the digital signal processor that the bus voltage is greater than the predetermined voltage and the output current is less than the predetermined current respectively, so that the digital signal processor turns off the secondary side rectifying circuit to stop outputting power.

Abstract: The present invention provides a manufacturing method for forming a semiconductor structure, in which first, a substrate is provided, a hard mask is disposed on the substrate, the hard mask is then patterned to form a plurality of fin hard masks and a plurality of dummy fin hard masks, afterwards, a pattern transferring process is performed, to transfer the patterns of the fin hard masks and the fin hard masks into the substrate, so as to form a plurality of fin groups and a plurality of dummy fins. Each dummy fin is disposed on the end side of one fin group, and a fin cut process is performed, to remove each dummy fin.

Abstract: A manufacturing method of a semiconductor structure is disclosed. The manufacturing method includes the following steps. A substrate with a plurality of dummy gate structures formed thereon and a first dielectric layer covering the dummy gate structures is provided, the dummy gate structures comprising a plurality of dummy gates and a plurality of insulating layers formed on the dummy gates, wherein at least two of the dummy gate structures have different heights. A first planarization process is performed to expose at least one of the dummy gate structures having the highest height. A first etching process is performed to expose the insulating layers. A chemical mechanical polishing (CMP) process with a non-selectivity slurry is performed to planarize the dummy gate structures. The planarized dummy gate structures are removed to form a plurality of gate trenches.

Abstract: A method of fabricating a semiconductor device includes the following steps. A substrate including at least a fin structure is provided, and a material layer is formed to cover the fin structure. Then, a first planarization process is performed on the material layer to form a first material layer, and an oxide layer is formed on the first material layer. Subsequently, the oxide layer is totally removed to expose the first material layer, and a second material layer is formed in-situ on the first material layer after totally removing the oxide layer.

Abstract: A method of fabricating a semiconductor device includes the following steps. A substrate including at least a fin structure is provided, and a material layer is formed to cover the fin structure. Then, a first planarization process is performed on the material layer to form a first material layer, and an oxide layer is formed on the first material layer. Subsequently, the oxide layer is totally removed to expose the first material layer, and a second material layer is formed in-situ on the first material layer after totally removing the oxide layer.

Abstract: The present invention provides a manufacturing method for forming a semiconductor structure, in which first, a substrate is provided, a hard mask is disposed on the substrate, the hard mask is then patterned to form a plurality of fin hard masks and a plurality of dummy fin hard masks, afterwards, a pattern transferring process is performed, to transfer the patterns of the fin hard masks and the fin hard masks into the substrate, so as to form a plurality of fin groups and a plurality of dummy fins. Each dummy fin is disposed on the end side of one fin group, and a fin cut process is performed, to remove each dummy fin.

Abstract: A semiconductor process includes the following steps. A substrate having trenches with different sizes is provided. A first oxide layer is formed to entirely cover the substrate. A prevention layer is formed on the first oxide layer. A first filling layer is formed on the prevention layer and fills the trenches until the first filling layer is higher than the substrate. A first polishing process is performed to polish the first filling layer until exposing the prevention layer. A second polishing process is performed to polish the first filling layer, the prevention layer and the first oxide layer until the substrate is exposed.

Abstract: A manufacturing method for a shallow trench isolation. First, a substrate is provided, a hard mask layer and a patterned photoresist layer are sequentially formed on the substrate, at least one trench is then formed in the substrate through an etching process, the hard mask layer is removed. Afterwards, a filler is formed at least in the trench and a planarization process is then performed on the filler. Since the planarization process is performed only on the filler, so the dishing phenomenon can effectively be avoided.

Abstract: A method of forming a semiconductor device is disclosed. A gate structure is formed on a substrate. The gate structure includes a dummy gate and a spacer at a sidewall of the dummy gate. A dielectric layer is formed on the substrate outside of the gate structure. A metal hard mask layer is formed to cover tops of the dielectric layer and the spacer and to expose a surface of the gate structure. The dummy gate is removed to form a gate trench. A low-resistivity metal layer is formed on the metal hard mask layer filling in the gate trench. The low-resistivity metal layer outside of the gate trench is removed. The metal hard mask layer is removed.

Abstract: A manufacturing method for a shallow trench isolation. First, a substrate is provided, a hard mask layer and a patterned photoresist layer are sequentially formed on the substrate, at least one trench is then formed in the substrate through an etching process, the hard mask layer is removed. Afterwards, a filler is formed at least in the trench and a planarization process is then performed on the filler. Since the planarization process is performed only on the filler, so the dishing phenomenon can effectively be avoided.

Abstract: A miniature wire antenna includes N rectangular metal plates located at a first layer of a PCB, a tunable metal plate located at the first layer of the PCB and N serpentine lines located at a second layer of the PCB. The positions of the N serpentine lines correspond to the positions of the rectangular metal plates. A first end of each of the serpentine lines is connected to the corresponding rectangular metal plate, and a second end of each of the serpentine lines is connected to the next rectangular metal plate. A first end of the last serpentine line is connected to the corresponding rectangular metal plate, and a second end of the last serpentine line is connected to the tunable metal plate.

Abstract: A planar antenna disposed on a plate having a first surface and a second surface is provided. The planar antenna includes a metal layer, an antenna body, a stepped impedance device, a coupling device and a matching device. The metal layer is disposed on the first surface and has a slot line exposing the first surface. The antenna body, the stepped impedance device, the coupling device and the matching device are disposed on the second surface. The antenna body is corresponding to a surrounding of the metal layer except a feed end thereof, the stepped impedance device and the matching device are corresponding to the metal layer, and the coupling device is corresponding to the slot line. The matching device is coupled between the coupling device and the feed end. The stepped impedance device has a transmission zero in a radio frequency band operated by the antenna body.