Patents by Inventor Chun-Hsu YEN
Chun-Hsu YEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240040939Abstract: A method for making a memory device, includes: forming a first dielectric layer over a bottom electrode; forming a first void extending through the first dielectric layer to expose a portion of an upper boundary of the bottom electrode; forming a first conductive structure lining along respective sidewalls of the first void and the exposed portion of the upper boundary of the bottom electrode; filling the first void with the first dielectric layer; and forming a phase change material layer over the first dielectric layer to cause the phase change material layer to contact at least a portion of a sidewall of the first conductive structure.Type: ApplicationFiled: August 8, 2023Publication date: February 1, 2024Inventors: Chun-Hsu Yen, Yu-Chuan Hsu, Chen-Hui Yang
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Patent number: 11784089Abstract: A semiconductor structure includes a conductive structure over a first passivation layer. The semiconductor structure further includes a second passivation layer over the conductive structure and the first passivation layer. The second passivation layer includes a first oxide film extending along a top surface of the first passivation layer, sidewalls and a top surface of the conductive structure, wherein a top surface of the first oxide film is planar. The second passivation layer further includes a second oxide film over a top surface of the first oxide film and a top surface of the conductive structure, wherein a top surface of the second oxide film is planar. The second passivation layer further includes a third oxide film extending along a top surface of the second oxide film, the sidewalls and the top surface of the conductive structure, wherein a top surface of the third oxide film is curved.Type: GrantFiled: July 14, 2022Date of Patent: October 10, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Hsu Yen, Chen-Hui Yang, Yu Chuan Hsu
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Patent number: 11765988Abstract: A method for making a memory device, includes: forming a first dielectric layer over a bottom electrode; forming a first void extending through the first dielectric layer to expose a portion of an upper boundary of the bottom electrode; forming a first conductive structure lining along respective sidewalls of the first void and the exposed portion of the upper boundary of the bottom electrode; filling the first void with the first dielectric layer; and forming a phase change material layer over the first dielectric layer to cause the phase change material layer to contact at least a portion of a sidewall of the first conductive structure.Type: GrantFiled: January 7, 2022Date of Patent: September 19, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Hsu Yen, Yu-Chuan Hsu, Chen-Hui Yang
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Publication number: 20220359276Abstract: A semiconductor structure includes a conductive structure over a first passivation layer. The semiconductor structure further includes a second passivation layer over the conductive structure and the first passivation layer. The second passivation layer includes a first oxide film extending along a top surface of the first passivation layer, sidewalls and a top surface of the conductive structure, wherein a top surface of the first oxide film is planar. The second passivation layer further includes a second oxide film over a top surface of the first oxide film and a top surface of the conductive structure, wherein a top surface of the second oxide film is planar. The second passivation layer further includes a third oxide film extending along a top surface of the second oxide film, the sidewalls and the top surface of the conductive structure, wherein a top surface of the third oxide film is curved.Type: ApplicationFiled: July 14, 2022Publication date: November 10, 2022Inventors: Chun-Hsu YEN, Chen-Hui YANG, Yu Chuan HSU
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Patent number: 11410878Abstract: A semiconductor structure includes a conductive structure over a first passivation layer; and a second passivation layer over the conductive structure and the first passivation layer. The second passivation layer has a first oxide film extending along a top surface of the first passivation layer, sidewalls and a top surface of the conductive structure, wherein a top surface of the first oxide film is planar. The second passivation layer further includes a second oxide film over a top surface of the first oxide film and a top surface of the conductive structure, wherein a top surface of the second oxide film is planar. The second passivation layer further includes a third oxide film extending along a top surface of the second oxide film, the sidewalls and the top surface of the conductive structure, wherein a top surface of the third oxide film is curved.Type: GrantFiled: January 7, 2021Date of Patent: August 9, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Hsu Yen, Yu Chuan Hsu, Chen-Hui Yang
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Publication number: 20220140235Abstract: A method for making a memory device, includes: forming a first dielectric layer over a bottom electrode; forming a first void extending through the first dielectric layer to expose a portion of an upper boundary of the bottom electrode; forming a first conductive structure lining along respective sidewalls of the first void and the exposed portion of the upper boundary of the bottom electrode; filling the first void with the first dielectric layer; and forming a phase change material layer over the first dielectric layer to cause the phase change material layer to contact at least a portion of a sidewall of the first conductive structure.Type: ApplicationFiled: January 7, 2022Publication date: May 5, 2022Inventors: Chun-Hsu YEN, Yu-Chuan HSU, Chen-Hui YANG
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Patent number: 11233197Abstract: A method for making a memory device, includes: forming a first dielectric layer over a bottom electrode; forming a first void extending through the first dielectric layer to expose a portion of an upper boundary of the bottom electrode; forming a first conductive structure lining along respective sidewalls of the first void and the exposed portion of the upper boundary of the bottom electrode; filling the first void with the first dielectric layer; and forming a phase change material layer over the first dielectric layer to cause the phase change material layer to contact at least a portion of a sidewall of the first conductive structure.Type: GrantFiled: November 19, 2019Date of Patent: January 25, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Hsu Yen, Yu-Chuan Hsu, Chen-Hui Yang
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Patent number: 11201122Abstract: A trench is formed through a plurality of layers that are disposed over a first substrate. A first deposition process is performed to at least partially fill the trench with a first dielectric layer. The first dielectric layer delivers a tensile stress. A second deposition process is performed to form a second dielectric layer over the first dielectric layer. A third deposition process is performed to form a third dielectric layer over the second dielectric layer. The third dielectric layer delivers a first compressive stress.Type: GrantFiled: February 7, 2019Date of Patent: December 14, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Hsu Yen, Yu Chuan Hsu, Chen-Hui Yang
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Publication number: 20210125860Abstract: A semiconductor structure includes a conductive structure over a first passivation layer; and a second passivation layer over the conductive structure and the first passivation layer. The second passivation layer has a first oxide film extending along a top surface of the first passivation layer, sidewalls and a top surface of the conductive structure, wherein a top surface of the first oxide film is planar. The second passivation layer further includes a second oxide film over a top surface of the first oxide film and a top surface of the conductive structure, wherein a top surface of the second oxide film is planar. The second passivation layer further includes a third oxide film extending along a top surface of the second oxide film, the sidewalls and the top surface of the conductive structure, wherein a top surface of the third oxide film is curved.Type: ApplicationFiled: January 7, 2021Publication date: April 29, 2021Inventors: Chun-Hsu YEN, Yu Chuan HSU, Chen-Hui YANG
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Patent number: 10923391Abstract: A semiconductor structure includes a conductive structure over a first passivation layer. The semiconductor structure further includes a second passivation layer over the conductive structure and the first passivation layer. The second passivation layer has a first oxide film extending along a top surface of the first passivation layer, sidewalls and a top surface of the conductive structure. The second passivation layer further includes a second oxide film over a top surface of the first oxide film and a top surface of the conductive structure. The second passivation layer further includes a third oxide film extending along a top surface of the second oxide film, the sidewalls and the top surface of the conductive structure.Type: GrantFiled: January 21, 2020Date of Patent: February 16, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Hsu Yen, Chen-Hui Yang, Yu Chuan Hsu
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Publication number: 20200161177Abstract: A semiconductor structure includes a conductive structure over a first passivation layer. The semiconductor structure further includes a second passivation layer over the conductive structure and the first passivation layer. The second passivation layer has a first oxide film extending along a top surface of the first passivation layer, sidewalls and a top surface of the conductive structure. The second passivation layer further includes a second oxide film over a top surface of the first oxide film and a top surface of the conductive structure. The second passivation layer further includes a third oxide film extending along a top surface of the second oxide film, the sidewalls and the top surface of the conductive structure.Type: ApplicationFiled: January 21, 2020Publication date: May 21, 2020Inventors: Chun-Hsu YEN, Chen-Hui YANG, Yu Chuan HSU
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Publication number: 20200105683Abstract: A trench is formed through a plurality of layers that are disposed over a first substrate. A first deposition process is performed to at least partially fill the trench with a first dielectric layer. The first dielectric layer delivers a tensile stress. A second deposition process is performed to form a second dielectric layer over the first dielectric layer. A third deposition process is performed to form a third dielectric layer over the second dielectric layer. The third dielectric layer delivers a first compressive stress.Type: ApplicationFiled: February 7, 2019Publication date: April 2, 2020Inventors: Chun-Hsu Yen, Yu Chuan Hsu, Chen-Hui Yang
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Publication number: 20200091423Abstract: A method for making a memory device, includes: forming a first dielectric layer over a bottom electrode; forming a first void extending through the first dielectric layer to expose a portion of an upper boundary of the bottom electrode; forming a first conductive structure lining along respective sidewalls of the first void and the exposed portion of the upper boundary of the bottom electrode; filling the first void with the first dielectric layer; and forming a phase change material layer over the first dielectric layer to cause the phase change material layer to contact at least a portion of a sidewall of the first conductive structure.Type: ApplicationFiled: November 19, 2019Publication date: March 19, 2020Inventors: Chun-Hsu YEN, Yu-Chuan Hsu, Chen-Hui Yang
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Patent number: 10553479Abstract: A method of fabricating a semiconductor structure includes forming a conductive structure over a first passivation layer, depositing a first dielectric film continuously over the conductive structure, depositing a second dielectric film continuously over the first dielectric film, and depositing a third dielectric film over the second dielectric film. A portion of the third dielectric film is in contact with a portion of the first dielectric film.Type: GrantFiled: September 12, 2017Date of Patent: February 4, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Hsu Yen, Chen-Hui Yang, Yu Chuan Hsu
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Patent number: 10510954Abstract: A memory device includes: a first conductive column structure extending through a first dielectric layer, wherein the first conductive column structure comprises a shell portion wrapping a core structure filled with a dielectric material and an end portion that is coupled to one end of the shell portion and disposed below the core structure; and a first phase change material layer formed over the first dielectric layer, wherein a lower boundary of the first phase change material layer contacts at least a first portion of the other end of the shell portion of the first conductive column structure.Type: GrantFiled: February 23, 2018Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Hsu Yen, Yu-Chuan Hsu, Chen-Hui Yang
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Publication number: 20190165265Abstract: A memory device includes: a first conductive column structure extending through a first dielectric layer, wherein the first conductive column structure comprises a shell portion wrapping a core structure filled with a dielectric material and an end portion that is coupled to one end of the shell portion and disposed below the core structure; and a first phase change material layer formed over the first dielectric layer, wherein a lower boundary of the first phase change material layer contacts at least a first portion of the other end of the shell portion of the first conductive column structure.Type: ApplicationFiled: February 23, 2018Publication date: May 30, 2019Inventors: Chun-Hsu Yen, Yu-Chuan Hsu, Chen-Hui Yang
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Publication number: 20180233466Abstract: A method of fabricating a semiconductor structure includes forming a conductive structure over a first passivation layer, depositing a first dielectric film continuously over the conductive structure, depositing a second dielectric film continuously over the first dielectric film, and depositing a third dielectric film over the second dielectric film. A portion of the third dielectric film is in contact with a portion of the first dielectric film.Type: ApplicationFiled: September 12, 2017Publication date: August 16, 2018Inventors: Chun-Hsu YEN, Chen-Hui YANG, Yu Chuan HSU
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Patent number: 9978634Abstract: A method for fabricating a shallow trench isolation includes forming a trench in a substrate, forming a bottom shallow trench isolation dielectric filling a gap of the trench, and forming a top shallow trench isolation dielectric on the bottom shallow trench isolation. The bottom shallow trench isolation dielectric has a concave center portion, and the top shallow trench isolation dielectric is deposited on the bottom shallow trench isolation by a high density plasma chemical vapor deposition process using low deposition to sputter ratio. A semiconductor structure having the shallow trench isolation is also disclosed.Type: GrantFiled: February 26, 2015Date of Patent: May 22, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Hsu Yen, Bang-Yu Huang, Chui-Ya Peng, Ching-Wen Chen
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Publication number: 20160254179Abstract: A method for fabricating a shallow trench isolation includes forming a trench in a substrate, forming a bottom shallow trench isolation dielectric filling a gap of the trench, and forming a top shallow trench isolation dielectric on the bottom shallow trench isolation. The bottom shallow trench isolation dielectric has a concave center portion, and the top shallow trench isolation dielectric is deposited on the bottom shallow trench isolation by a high density plasma chemical vapor deposition process using low deposition to sputter ratio. A semiconductor structure having the shallow trench isolation is also disclosed.Type: ApplicationFiled: February 26, 2015Publication date: September 1, 2016Inventors: Chun-Hsu YEN, Bang-Yu HUANG, Chui-Ya PENG, Ching-Wen CHEN