Patents by Inventor CHUN-HSUAN LIN

CHUN-HSUAN LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250149524
    Abstract: A package structure includes a frontside redistribution layer (RDL) structure with a recessed portion, a lower encapsulation layer on the frontside RDL structure and a plurality of through vias connected to the frontside RDL structure to an upper package, a first semiconductor die on the frontside RDL structure and in the lower encapsulation layer, and an integrated passive device (IPD) connected to the frontside RDL structure in the recessed portion that connects to the first semiconductor die. A method of forming a package structure includes forming a molded portion with a lower encapsulation layer, a plurality of through vias in the lower encapsulation layer and a first semiconductor die in the lower encapsulation layer, forming a RDL structure with a recessed portion on the molded portion, the plurality of through vias connect the frontside RDL structure to an upper package, and attaching an IPD in the recessed portion.
    Type: Application
    Filed: November 3, 2023
    Publication date: May 8, 2025
    Inventors: Chun-Sheng Fan, Ta-Hsuan Lin, Hua-Wei Tseng, Wei-Cheng Wu
  • Publication number: 20250140643
    Abstract: A package structure is provided. The package structure comprises a package substrate, an electronic device, a thermal interface material (TIM), a lid and an insulating encapsulant. The electronic device is disposed on and electrically connected to the package substrate. The TIM is disposed on the electronic device. The lid is disposed on the TIM. The insulating encapsulant is disposed on the package substrate and laterally encapsulates the electronic device and the TIM. A lateral dimension of the TIM is greater than a lateral dimension of the electronic device.
    Type: Application
    Filed: November 1, 2023
    Publication date: May 1, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Wei Li, Chun-Yen Lan, Yu-Wei Lin, Sheng-Hsiang Chiu, Tzu-Ting Chou, Pei-Hsuan Lee, Chih-Wei Lin, Ching-Hua Hsieh
  • Publication number: 20250137955
    Abstract: An environment detection apparatus is provided. In one embodiment, the detection apparatus comprises: a first sensing device, a second sensing device in fluid communication with the first sensing device and a spectrum analyzer electrically connected to the first sensing device and the second sensing device. The first sensing device includes a pair of first electrodes configured to provide a first alternating current signal directly to a gas flowing into the first sensing device. The second sensing device includes a first filter configured to capture a solid in the gas flowing into the second sensing device and a pair of second electrodes configured to provide a second alternating current signal directly to the first filter with the solid captured by the first filter.
    Type: Application
    Filed: October 26, 2023
    Publication date: May 1, 2025
    Inventors: MING DA YANG, CHUN-HSUAN LIN, CHWEN YU
  • Publication number: 20250130935
    Abstract: A device control method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: establishing a connection between the memory storage device and a host system; performing a first communication with the host system based on the connection and a first connection interface standard; performing a data recovery operation between the memory storage device and the host system via the connection during a period of performing the first communication; and switching to perform a second communication with the host system based on the connection and a second connection interface standard in a case that the data recovery operation is successfully performed, wherein the first connection interface standard is different from the second connection interface standard.
    Type: Application
    Filed: November 28, 2023
    Publication date: April 24, 2025
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Yuwei Kuo, Hung Yuan Tsai, Chun Ming Liu, Yu Hsuan Chen, Yun-You Lin
  • Patent number: 12278208
    Abstract: A method of fabricating a semiconductor structure includes the following steps. A semiconductor wafer is provided. A plurality of first surface mount components and a plurality of second surface mount components are bonded onto the semiconductor wafer, wherein a first portion of each of the second surface mount components is overhanging a periphery of the semiconductor wafer. A first barrier structure is formed in between the second surface mount components and the semiconductor wafer. An underfill structure is formed under a second portion of each of the second surface mount components, wherein the first barrier structure blocks the spreading of the underfill structure from the second portion to the first portion.
    Type: Grant
    Filed: November 1, 2023
    Date of Patent: April 15, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mao-Yen Chang, Chih-Wei Lin, Hao-Yi Tsai, Kuo-Lung Pan, Chun-Cheng Lin, Tin-Hao Kuo, Yu-Chia Lai, Chih-Hsuan Tai
  • Patent number: 12269975
    Abstract: A composite film includes a first thermoplastic elastomer film layer and a second thermoplastic elastomer film layer, wherein the first thermoplastic elastomer film layer includes a first styrenic block copolymer. The second thermoplastic elastomer film layer is disposed on the first thermoplastic elastomer film layer, wherein the second thermoplastic elastomer film layer includes a second styrenic block copolymer, diffusion particles dispersed in the second thermoplastic elastomer film layer, and a surface microstructure disposed on the surface of the second thermoplastic elastomer film layer.
    Type: Grant
    Filed: April 27, 2023
    Date of Patent: April 8, 2025
    Assignee: Industrial Technology Research Institute
    Inventors: Cheng-Hsuan Lin, Yu-Ling Hsu, Chun-Chen Chiang, Yi-Ping Chen
  • Publication number: 20250110164
    Abstract: An electrostatic field strength measuring apparatus includes an electrostatic field detection device and a processor. The electrostatic field detection device includes a ring light source configured to emit a light signal to a target object, and a reflection detector disposed within and surrounded by the ring light source and configured to receive a reflection signal, of the light signal, reflected by a surface of the target object and generate an electrical signal based upon the reflection signal. The processor is configured to determine, based upon the electrical signal, measures of electrostatic field strength at the surface of the target object.
    Type: Application
    Filed: October 3, 2023
    Publication date: April 3, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming Da Yang, Chun-Hsuan Lin, Yi-Chen Li
  • Publication number: 20250076369
    Abstract: A minimum IC operating voltage searching method includes acquiring a corner type of an IC, acquiring ring oscillator data of the IC, generating a first prediction voltage according to the corner type and the ring oscillator data by using a training model, generating a second prediction voltage according to the ring oscillator data by using a non-linear regression approach under an N-ordered polynomial, and generating a predicted minimum IC operating voltage according to the first prediction voltage and the second prediction voltage. N is a positive integer.
    Type: Application
    Filed: April 16, 2024
    Publication date: March 6, 2025
    Applicant: MEDIATEK INC.
    Inventors: Ronald Kuo-Hua Ho, Kun-Yu Wang, Yen-Chang Shih, Sung-Te Chen, Cheng-Han Wu, Yi-Ying Liao, Chun-Ming Huang, Yen-Feng Lu, Ching-Yu Tsai, Tai-Lai Tung, Kuan-Fu Lin, Bo-Kang Lai, Yao-Syuan Lee, Tsyr-Rou Lin, Ming-Chao Tsai, Li-Hsuan Chiu
  • Patent number: 12242321
    Abstract: The disclosure provides a power management method. The power management method is applicable to an electronic device. The electronic device is electrically coupled to an adapter, and includes a system and a battery. The adapter has a feed power. The battery has a discharge power. The power management method of the disclosure includes: reading a power value of the battery; determining a state of the system; and discharging power to the system, when the system is in a power-on state and the power value is greater than a charging stopping value, by using the battery, and controlling, according to the discharge power and the feed power, the adapter to selectively supply power to the system. The disclosure further provides an electronic device using the power management method.
    Type: Grant
    Filed: April 27, 2023
    Date of Patent: March 4, 2025
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Wen Che Chung, Hui Chuan Lo, Hao-Hsuan Lin, Chun Tsao, Jun-Fu Chen, Ming-Hung Yao, Jia-Wei Zhang, Kuan-Lun Chen, Ting-Chao Lin, Cheng-Yen Lin, Chunyen Lai
  • Publication number: 20250066899
    Abstract: A method includes: positioning a wafer on an electrostatic chuck of a physical vapor deposition apparatus, the wafer including an opening exposing a conductive feature; setting a temperature of the wafer to a room temperature; forming a tungsten thin film in the opening by the physical vapor deposition apparatus, the tungsten thin film including a bottom portion that is on an upper surface of the conductive feature exposed by the opening, a top portion that is on an upper surface of a dielectric layer through which the opening extends and a sidewall portion that is on a sidewall of the dielectric layer exposed by the opening; removing the top portion and the sidewall portion of the tungsten thin film from over the opening; and forming a tungsten plug in the opening on the bottom portion by selectively depositing tungsten by a chemical vapor deposition operation.
    Type: Application
    Filed: August 23, 2023
    Publication date: February 27, 2025
    Inventors: Chun-Yen LIAO, I. LEE, Shu-Lan CHANG, Sheng-Hsuan LIN, Feng-Yu CHANG, Wei-Jung LIN, Chun-I TSAI, Chih-Chien CHI, Ming-Hsing TSAI, Pei Shan CHANG, Chih-Wei CHANG
  • Patent number: 12237415
    Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an epitaxial layer adjacent to the gate structure, and then forming a first cap layer on the epitaxial layer. Preferably, a top surface of the first cap layer includes a curve concave upward and a bottom surface of the first cap layer includes a planar surface higher than a top surface of the substrate.
    Type: Grant
    Filed: August 17, 2023
    Date of Patent: February 25, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chi-Hsuan Tang, Chung-Ting Huang, Bo-Shiun Chen, Chun-Jen Chen, Yu-Shu Lin
  • Publication number: 20250062202
    Abstract: A semiconductor die and methods of forming the same and a package structure are provided. The semiconductor die includes a semiconductor substrate, a plurality of conductive pads over the semiconductor substrate, a passivation layer over the semiconductor substrate and partially covering the plurality of conductive pads, an interconnecting line disposed on the passivation layer, and a plurality of connectors disposed on and electrically connected to the plurality of conductive pads. Each of the plurality of connectors includes a stacked structure of a first conductive pillar and a second conductive pillar disposed directly on the first conductive pillar, wherein a span of the second conductive pillar is smaller than a span of the first conductive pillar, and an orthogonal projection of the second conductive pillar falls within an orthogonal projection of the first conductive pillar, and the interconnecting line is located beside and spaced apart from the plurality of connectors.
    Type: Application
    Filed: August 17, 2023
    Publication date: February 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Yi Sung, Ta-Hsuan Lin, Hua-Wei Tseng, Mill-Jer Wang
  • Publication number: 20240118329
    Abstract: An apparatus is provided. The apparatus includes a laser generation device configured to emit a laser signal to a semiconductor fabrication component. The apparatus includes a reflection detection device configured to receive a reflection signal comprising light, of the laser signal, reflected by a surface of the semiconductor fabrication component. The reflection detection device includes an optical filter. The optical filter is configured to block light, of the reflection signal, that has a wavelength outside a defined range of wavelengths. The optical filter is configured to provide filtered light, from the reflection signal, that has a wavelength within the defined range of wavelengths. The reflection detection device includes a light sensor configured to generate an electrical signal based upon the filtered light. The apparatus includes a computer configured to determine, based upon the electrical signal, measures of electrostatic field strength at the surface of the semiconductor fabrication component.
    Type: Application
    Filed: May 11, 2023
    Publication date: April 11, 2024
    Inventors: Ming Da YANG, Yi-Chen LI, Chun-Hsuan LIN
  • Patent number: 9191729
    Abstract: An earphone with adjustable-length cable includes a plugging section, a connecting cable and a receiving section. The plugging section has an attach-conductive adapter and a plug at two ends respectively. The connecting cable connects the plugging section and the receiving section, and has at least one separable attaching cable. The separable attaching cable has two attach-conductive adapters at two ends respectively. The receiving section has an attach-conductive adapter and an audio-playing unit at two ends respectively. Each attach-conductive adapter is formed with an end surface, and has at least one attaching element and a plurality of conductive plates exposed at outside of the end surface. The attach-conductive adapters are attached each other by the attaching elements, and electrically connected to each other through the conductive plates, so that signals from the plugging section are transmitted to the receiving section and are played by the audio-playing unit.
    Type: Grant
    Filed: May 10, 2014
    Date of Patent: November 17, 2015
    Inventor: Chun-Hsuan Lin
  • Publication number: 20150215694
    Abstract: An earphone with adjustable-length cable includes a plugging section, a connecting cable and a receiving section. The plugging section has an attach-conductive adapter and a plug at two ends respectively. The connecting cable connects the plugging section and the receiving section, and has at least one separable attaching cable. The separable attaching cable has two attach-conductive adapters at two ends respectively. The receiving section has an attach-conductive adapter and an audio-playing unit at two ends respectively. Each attach-conductive adapter is formed with an end surface, and has at least one attaching element and a plurality of conductive plates exposed at outside of the end surface. The attach-conductive adapters are attached each other by the attaching elements, and electrically connected to each other through the conductive plates, so that signals from the plugging section are transmitted to the receiving section and are played by the audio-playing unit.
    Type: Application
    Filed: May 10, 2014
    Publication date: July 30, 2015
    Inventor: CHUN-HSUAN LIN