Abstract: A device includes: alternating first rows and second rows correspondingly including first cell regions and second cell regions, each of the first cell regions and second cell regions correspondingly including active regions; in a first metallization layer over the active regions, each of the first cell regions and the second cell regions include first and second power grid (PG) segments, and one or more routing (RTE) segments; and in a first buried metallization layer under the active regions, each of the first cell regions includes first and second buried PG (BPG) segments, and each of the second cell regions includes one or more buried local interconnect (BLI) structures; and each of the first cell regions is free from including a BLI structure.

Abstract: An integrated circuit device includes a first semiconductor layer, a second semiconductor layer, a first source/drain epitaxial structure, a second source/drain epitaxial structure, and a first contact plug. The second semiconductor layer is above the first semiconductor layer. The first and second semiconductor layers are vertically spaced apart from each other. The first source/drain epitaxial structure is on a side of the first semiconductor layer. The second source/drain epitaxial structure is on a side of the second semiconductor layer and above the first source/drain epitaxial structure. The first source/drain epitaxial structure has a portion extending beyond a sidewall of the second source/drain epitaxial structure from a top view. The first contact plug is over a frontside of the first source/drain epitaxial structure. The first contact plug overlaps the portion of the first source/drain epitaxial structure from the top view.

Abstract: A rectangular parallelepiped (RP) cell region includes: a 3D L-shape region, a dummy region and a resident region each of which includes transistor components, transistors of the resident region being free from comprising a function of the L-shape region; the dummy region and the resident region being in first notch formed by an arm and a stem of the L-shape region; first type transistors of the arm being stacked correspondingly over second type transistors of the first part of the stem; dummy transistor(s) of the dummy region being stacked over second type transistors of the second part of the stem; and first type transistors of the resident region being stacked over second type transistors of the third part of the stem.