Abstract: The present disclosure, in some embodiments, relates to a method of forming a capacitor structure. The method includes forming a capacitor dielectric layer over a lower electrode layer, and forming an upper electrode layer over the capacitor dielectric layer. The upper electrode layer is etched to define an upper electrode and to expose a part of the capacitor dielectric layer. A spacer structure is formed over horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and also along sidewalls of the upper electrode. The spacer structure is etched to remove the spacer structure from over the horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and to define a spacer. The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define a capacitor dielectric and a lower electrode.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a dielectric structure sandwiched between a first electrode and a bottom electrode. A passivation layer overlies the second electrode and the dielectric structure. The passivation layer comprises a horizontal surface vertically below a top surface of the passivation layer. The horizontal surface is disposed above a top surface of the dielectric structure.

Abstract: The present disclosure relates to an integrated chip including a dielectric structure over a substrate. A first capacitor is disposed between sidewalls of the dielectric structure. The first capacitor includes a first electrode between the sidewalls of the dielectric structure and a second electrode between the sidewalls and over the first electrode. A second capacitor is disposed between the sidewalls. The second capacitor includes the second electrode and a third electrode between the sidewalls and over the second electrode. A third capacitor is disposed between the sidewalls. The third capacitor includes the third electrode and a fourth electrode between the sidewalls and over the third electrode. The first capacitor, the second capacitor, and the third capacitor are coupled in parallel by a first contact on a first side of the first capacitor and a second contact on a second side of the first capacitor.

Abstract: Systems, devices, methods, and circuits for managing content addressable memory (CAM) devices. In one aspect, a semiconductor device includes: a memory cell array configured to store data in memory cells, and a circuitry coupled to the memory cell array and configured to execute a search operation in the memory cell array according to a search instruction. The search instruction includes at least one of search data or an option code, and the option code specifies, for the search operation, at least one of a search length or a search depth.

Abstract: In some embodiments, the present disclosure relates to a device having a semiconductor substrate including a frontside and a backside. On the frontside of the semiconductor substrate are a first source/drain region and a second source/drain region. A gate electrode is arranged on the frontside of the semiconductor substrate and includes a horizontal portion, a first vertical portion, and a second vertical portion. The horizontal portion is arranged over the frontside of the semiconductor substrate and between the first and second source/drain regions. The first vertical portion extends from the frontside towards the backside of the semiconductor substrate and contacts the horizontal portion of the gate electrode structure. The second vertical portion extends from the frontside towards the backside of the semiconductor substrate, contacts the horizontal portion of the gate electrode structure, and is separated from the first vertical portion by a channel region of the substrate.

Abstract: A method of forming a semiconductor device includes forming an opening in a dielectric layer, and forming a barrier layer in the opening. A combined liner layer is formed over the barrier layer by first forming a first liner layer over the barrier layer, and forming a second liner layer over the first liner layer, such that the first liner layer and the second liner layer intermix. A conductive material layer is formed over the combined liner layer, and a thermal process is performed to reflow the conductive material layer.

Abstract: A first transistor includes a first gate, a first source/drain, and a first source/drain contact disposed over the first source/drain. The first gate has a first dimension measured in a first lateral direction. The first source/drain contact has a second dimension measured in the first lateral direction. A second transistor includes a second gate, a second source/drain, and a second source/drain contact disposed over the second source/drain. The second gate has a third dimension measured in the first lateral direction. The second source/drain contact has a fourth dimension measured in the first lateral direction. A first ratio of the first dimension and the second dimension is different from a second ratio of the third dimension and the fourth dimension.

Abstract: The present disclosure relates to an integrated chip including a dielectric structure over a substrate. A first capacitor is disposed between sidewalls of the dielectric structure. The first capacitor includes a first electrode between the sidewalls of the dielectric structure and a second electrode between the sidewalls and over the first electrode. A second capacitor is disposed between the sidewalls. The second capacitor includes the second electrode and a third electrode between the sidewalls and over the second electrode. A third capacitor is disposed between the sidewalls. The third capacitor includes the third electrode and a fourth electrode between the sidewalls and over the third electrode. The first capacitor, the second capacitor, and the third capacitor are coupled in parallel by a first contact on a first side of the first capacitor and a second contact on a second side of the first capacitor.

Abstract: The present invention provides capacitor-based fluid sensing units. The capacitor-based fluid sensing unit comprises a substrate, a first electrode configured on the substrate, a sensing layer configured on the first electrode, a second electrode configured on the sensing layer. More particularly, the second electrode is a porous electrode, while the sensing layer is made of a porous dielectric material and has a thickness between 50 nm and 5 mm. Permittivity of the sensing layer changes as fluid permeates from the second electrode to the sensing layer. The subsequent change in capacitance of the capacitor-based fluid sensing unit is used to determine the volume of the fluid.

Abstract: Light-addressable potentiometric sensing units are provided. A light-addressable potentiometric sensing unit comprises a conductive substrate, a metal oxide semiconductor layer, and a sensing layer. The metal oxide semiconductor layer is made of indium gallium zinc oxide, indium gallium oxide, indium zinc oxide, indium oxide co-doped with tin and zinc, tin oxide, or zinc oxide. The wide-band gap characteristic of the metal oxide semiconductor layer enables the light-addressable potentiometric sensing unit to resist the interference from visible light. The light-addressable potentiometric sensing unit therefore exhibits a more stable performance.

Abstract: The present invention provides a data storage device including a flash memory and a controller. The controller is configured to perform a first read operation to read a first page corresponding to a first word line of the flash memory according to a read command of a host, and perform a distribution-adjustment procedure when data read by the first read operation cannot be recovered by coding, wherein the controller is further configured to perform an adjustable read operation to read a second page corresponding to a second word line of the flash memory in the distribution-adjustment procedure.

Abstract: The present invention provides capacitor-based fluid sensing units. The capacitor-based fluid sensing unit comprises a substrate, a first electrode configured on the substrate, a sensing layer configured on the first electrode, a second electrode configured on the sensing layer. More particularly, the second electrode is a porous electrode, while the sensing layer is made of a porous dielectric material and has a thickness between 50 nm and 5 mm. Permittivity of the sensing layer changes as fluid permeates from the second electrode to the sensing layer. The subsequent change in capacitance of the capacitor-based fluid sensing unit is used to determine the volume of the fluid.

Abstract: Light-addressable potentiometric sensing units are provided. A light-addressable potentiometric sensing unit comprises a conductive substrate, a metal oxide semiconductor layer, and a sensing layer. The metal oxide semiconductor layer is made of indium gallium zinc oxide, indium gallium oxide, indium zinc oxide, indium oxide co-doped with tin and zinc, tin oxide, or zinc oxide. The wide-band gap characteristic of the metal oxide semiconductor layer enables the light-addressable potentiometric sensing unit to resist the interference from visible light. The light-addressable potentiometric sensing unit therefore exhibits a more stable performance.

Abstract: The present invention provides a data storage device including a flash memory and a controller. The controller is configured to perform a first read operation to read a first page corresponding to a first word line of the flash memory according to a read command of a host, and perform a distribution-adjustment procedure when data read by the first read operation cannot be recovered by coding, wherein the controller is further configured to perform an adjustable read operation to read a second page corresponding to a second word line of the flash memory in the distribution-adjustment procedure.

Abstract: The present invention provides a data storage device including a flash memory and a controller. The controller is configured to perform a first read operation to read a first page corresponding to a first word line of the flash memory according to a read command of a host, and perform a distribution-adjustment procedure when data read by the first read operation cannot be recovered by coding, wherein the controller is further configured to perform an adjustable read operation to read a second page corresponding to a second word line of the flash memory in the distribution-adjustment procedure.

Abstract: The present invention provides a data storage device including a flash memory and a controller. The controller is configured to perform a first read operation to read a first page corresponding to a first word line of the flash memory according to a read command of a host, and perform a distribution-adjustment procedure when data read by the first read operation cannot be recovered by coding, wherein the controller is further configured to perform an adjustable read operation to read a second page corresponding to a second word line of the flash memory in the distribution-adjustment procedure.

Abstract: A paper clip made of a resilient steel wire bent into shape, which comprises two front bends disposed at same plane and formed into a clamping portion for holding sheets of paper inserted therebetween, and an unitary wave-like back bend substantially perpendicular to the two front bends and forming a stop portion for stopping the paper which is fastened in the clamping portion. The wave-like back bend is formed of at least one peak and one wave trough so as to provide stronger tensile elasticity permitting the clamping portion to tightly retain more sheets of paper.