Patents by Inventor Chun Hui Low
Chun Hui Low has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8354347Abstract: A composite etch stop layer which comprises primary and secondary stop layers is used to form contacts in a dielectric layer to contact regions in a substrate. The secondary etch stop layer includes a high-k dielectric material to achieve high etch selectivity with the dielectric layer during contact formation. The secondary stop layer is removed to expose the contact regions. Removal of the secondary stop layer is achieved with high selectivity to the materials therebelow.Type: GrantFiled: December 11, 2007Date of Patent: January 15, 2013Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Jianhui Ye, Huang Liu, Alex K H See, Wei Lu, Chun Hui Low, Chim Seng Seet, Mei Sheng Zhou, Liang Choo Hsia
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Patent number: 8293545Abstract: Test structures including test trenches are used to define critical dimension of trenches in a via level of an integrated circuit to produce substantially the same depth. The trenches are formed at the periphery of the IC to serve as guard rings.Type: GrantFiled: October 29, 2007Date of Patent: October 23, 2012Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Hai Cong, Yan Shan Li, Chun Hui Low, Yelehanka Ramachandramurthy Pradeep, Liang Choo Hsia
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Patent number: 7781895Abstract: An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.Type: GrantFiled: June 17, 2009Date of Patent: August 24, 2010Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Bei Chao Zhang, Chun Hui Low, Hong Lim Lee, Sang Yee Loong, Qiang Guo
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Patent number: 7691739Abstract: An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.Type: GrantFiled: March 13, 2006Date of Patent: April 6, 2010Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Bei Chao Zhang, Chun Hui Low, Hong Lim Lee, Sang Yee Loong, Qiang Guo
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Publication number: 20090250818Abstract: An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.Type: ApplicationFiled: June 17, 2009Publication date: October 8, 2009Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Bei Chao Zhang, Chun Hui Low, Hong Lim Lee, Sang Yee Loong, Qiang Guo
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Publication number: 20090146296Abstract: A composite etch stop layer which comprises primary and secondary stop layers is used to form contacts in a dielectric layer to contact regions in a substrate. The secondary etch stop layer includes a high-k dielectric material to achieve high etch selectivity with the dielectric layer during contact formation. The secondary stop layer is removed to expose the contact regions. Removal of the secondary stop layer is achieved with high selectivity to the materials therebelow.Type: ApplicationFiled: December 11, 2007Publication date: June 11, 2009Applicant: Chartered Semiconductor Manufacturing, Ltd.Inventors: Jianhui YE, Huang LIU, Alex KH SEE, Wei LU, Chun Hui LOW, Chim Seng SEET, Mei Sheng ZHOU, Liang Choo HSIA
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Publication number: 20090108257Abstract: Test structures including test trenches are used to define critical dimension of trenches in a via level of an integrated circuit to produce substantially the same depth. The trenches are formed at the periphery of the IC to serve as guard rings.Type: ApplicationFiled: October 29, 2007Publication date: April 30, 2009Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.Inventors: Hai Cong, Yan San Li, Chun Hui Low, Yelehanka Ramachandramurthy Pradeep, Liang Choo Hsia
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Patent number: 7352064Abstract: Methods of forming a metal line and/or via critical dimension (CD) in a single or dual damascene process on a semiconductor substrate, and the resist scheme implemented, are disclosed. The method includes forming a multiple layer resist scheme including a first planarizing layer of a first type material over the substrate, a second dielectric layer of a second type material over the planarizing layer, and a third photoresist layer of a third type material over the dielectric layer. The types of material alternate between organic and inorganic material. The third layer is patterned for the metal line and/or via CD. Sequential etching to form the metal line and/or via critical dimension using a tailored etch recipe particular to each of the first photoresist layer, the second dielectric layer and the third planarizing layer as each layer is exposed is then used. Accurate CD formation and adequate resist budget are provided.Type: GrantFiled: November 4, 2004Date of Patent: April 1, 2008Assignee: International Business Machines CorporationInventors: Nicholas C. M. Fuller, Timothy J. Dalton, Raymond Joy, Yi-hsiung Lin, Chun Hui Low
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Patent number: 7045455Abstract: An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.Type: GrantFiled: October 23, 2003Date of Patent: May 16, 2006Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Beichao Zhang, Chun Hui Low, Hong Lim Lee, Sang Yee Loong, Qiang Guo
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Patent number: 6350661Abstract: An improved and new process for fabricating MOSFET's in shallow trench isolation (STI), with sub-quarter micron ground rules, includes a passivating trench cap layer of silicon nitride. The silicon nitride passivating trench cap is utilized in the formation of borderless or “unframed” electrical contacts, without reducing the poly to poly spacing. Borderless contacts are formed, wherein contact openings are etched in an interlevel dielectric (ILD) layer over both an active region (P-N junction) and an inactive trench isolation region. During the contact hole opening, a selective etch process is utilized which etches the ILD layer, while the protecting passivating silicon nitride trench cap layer remains intact protecting the P-N junction at the edge of trench region. Subsequent processing of conductive tungsten metal plugs are prevented from shorting by the passivating trench cap.Type: GrantFiled: June 18, 2001Date of Patent: February 26, 2002Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Chong Wee Lim, Eng Hua Lim, Soh Yun Siah, Kong Hean Lee, Chun Hui Low
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Publication number: 20010031540Abstract: An improved and new process for fabricating MOSFET's in shallow trench isolation (STI), with sub-quarter micron ground rules, includes a passivating trench cap layer of silicon nitride. The silicon nitride passivating trench cap is utilized in the formation of borderless or “unframed” electrical contacts, without reducing the poly to poly spacing. Borderless contacts are formed, wherein contact openings are etched in an interlevel dielectric (ILD) layer over both an active region (P-N junction) and an inactive trench isolation region. During the contact hole opening, a selective etch process is utilized which etches the ILD layer, while the protecting passivating silicon nitride trench cap layer remains intact protecting the P-N junction at the edge of trench region. Subsequent processing of conductive tungsten metal plugs are prevented from shorting by the passivating trench cap.Type: ApplicationFiled: June 18, 2001Publication date: October 18, 2001Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Chong Wee Lim, Eng Hua Lim, Soh Yun Siah, Kong Hean Lee, Chun Hui Low
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Patent number: 6297126Abstract: An improved and new process for fabricating MOSFET's in shallow trench isolation (STI), with sub-quarter micron ground rules, includes a passivating trench cap layer of silicon nitride. The silicon nitride passivating trench cap is utilized in the formation of borderless or “unframed” electrical contacts, without reducing the poly to poly spacing. Borderless contacts are formed, wherein contact openings are etched in an interlevel dielectric (ILD) layer over both an active region (P-N junction) and an inactive trench isolation region. During the contact hole opening, a selective etch process is utilized which etches the ILD layer, while the protecting passivating silicon nitride trench cap layer remains intact protecting the P-N junction at the edge of trench region. Subsequent processing of conductive tungsten metal plugs are prevented from shorting by the passivating trench cap.Type: GrantFiled: July 12, 1999Date of Patent: October 2, 2001Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Chong Wee Lim, Eng Hua Lim, Soh Yun Siah, Kong Hean Lee, Chun Hui Low
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Patent number: 6271133Abstract: A new method is established to form different silicide layers over the top of the gate electrode and the surface of the source/drain regions. A thin layer of TiSi2 is formed over the source/drain regions by depositing a layer of titanium and annealing this layer with the silicon substrate. The gate electrode is created as a recessed electrode, in the top recession of the electrode a layer of CoSi2 is formed by depositing a layer of cobalt over the gate electrode. This layer of COSi2 serves as the electrical gate contact point.Type: GrantFiled: April 12, 1999Date of Patent: August 7, 2001Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Chong Wee Lim, Eng Hua Lim, Kin Leong Pey, Soh Yun Siah, Chun Hui Low
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Patent number: 6265302Abstract: An improved and new process for fabricating MOSFET's in shallow trench isolation (STI), with sub-quarter micron ground rules, includes a passivating trench liner of silicon nitride. The silicon nitride passivating liner is utilized in the formation of borderless or “unframed” electrical contacts, without reducing the poly to poly spacing. Borderless contacts are formed, wherein contact openings are etched in an interlevel dielectric (ILD) layer over both an active region (P-N junction) and an inactive trench isolation region. During the contact hole opening, a selective etch process is utilized which etches the ILD layer, while the protecting passivating silicon nitride liner remains intact protecting the P-N junction at the edge of trench region. Subsequent processing of conductive tungsten metal plugs are prevented from shorting by the passivating trench liner.Type: GrantFiled: July 12, 1999Date of Patent: July 24, 2001Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Chong Wee Lim, Eng Hua Lim, Soh Yun Siah, Kong Hean Lee, Chun Hui Low
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Patent number: 6228727Abstract: A method of fabricating shallow trench isolations has been achieved. A semiconductor substrate is provided. A pad oxide layer is grown overlying the semiconductor substrate. A silicon nitride layer is deposited. The silicon nitride layer and the pad oxide layer are patterned to form a hard mask. The openings in the hard mask correspond to planned trenches in the semiconductor substrate. A silicon dioxide layer is deposited overlying the silicon nitride layer and the semiconductor substrate. The silicon dioxide layer is anisotropically etched to form sidewall spacers on the inside of the openings of the hard mask. The semiconductor substrate is etched to form the trenches. The sidewall spacers are etched away. The semiconductor substrate is sputter etched to round the corners of the trenches. An oxide trench lining layer is grown overlying the semiconductor substrate. A trench fill layer is deposited overlying the silicon nitride layer and filling the trenches.Type: GrantFiled: September 27, 1999Date of Patent: May 8, 2001Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Chong Wee Lim, Soh Yun Siah, Eng Hua Lim, Kong-Hean Lee, Chun Hui Low