Patents by Inventor Chun Hui Yu

Chun Hui Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240379305
    Abstract: A key structure includes a keycap, a connecting member, a fixing member, a light emitter and a light receiver. The connecting member is connected to an inner top surface of the keycap and extends downwards, and the connecting member has a first opening through the connecting member. The fixing member has a second opening through the fixing member, in which when the keycap is initially pressed and then continues to be pressed, the keycap moves in a direction, and the connecting member moves with the keycap, and an overlapping region defined by the first opening and the second opening gradually becomes larger or smaller. The light emitter is laterally adjacent to the second opening of the fixing member. The light receiver is laterally adjacent to the first opening of the connecting member.
    Type: Application
    Filed: June 30, 2023
    Publication date: November 14, 2024
    Inventors: Chien-Pang Chien, Tsu-Hui Yu, Tao-Ying Chen, Chun-Nan Su, Chun-Che Wu
  • Publication number: 20240355756
    Abstract: Provided is a method of fabricating a package including: providing a die with a contact thereon; forming a redistribution layer (RDL) structure on the die, the forming the RDL structure on the die comprising: forming a first dielectric material on the die; forming a conductive feature in and partially on the first dielectric material; after the forming the conductive feature, forming a protective layer on the conductive feature, wherein the protective layer covers a top surface of the conductive feature and extends to cover a top surface of the first dielectric material; forming a second dielectric material on the protective layer; and performing a planarization process to expose the conductive feature; and forming a plurality of conductive connectors to electrically connect the die through the RDL structure.
    Type: Application
    Filed: July 3, 2024
    Publication date: October 24, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Kuo-Chung Yee, Chun-Hui Yu
  • Patent number: 12057406
    Abstract: Provided is a package including: a die having an upper surface and including at least one conductive pad disposed adjacent to the upper surface; a first pillar structure over the die; and a second pillar structure aside the first pillar structure, wherein the second pillar structure is electrically connected to the conductive pad of the die, and defining a recess portion recessed from a side surface of the second pillar structure, wherein the second pillar structure and the conductive pad have different conductivities.
    Type: Grant
    Filed: June 6, 2022
    Date of Patent: August 6, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Kuo-Chung Yee, Chun-Hui Yu
  • Patent number: 12014993
    Abstract: Provided is a method of fabricating a package including: providing a die with a contact thereon; forming a redistribution layer (RDL) structure on the die, the forming the RDL structure on the die comprising: forming a first dielectric material on the die; forming a conductive feature in and partially on the first dielectric material; after the forming the conductive feature, forming a protective layer on the conductive feature, wherein the protective layer covers a top surface of the conductive feature and extends to cover a top surface of the first dielectric material; forming a second dielectric material on the protective layer; and performing a planarization process to expose the conductive feature; and forming a plurality of conductive connectors to electrically connect the die through the RDL structure.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: June 18, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Kuo-Chung Yee, Chun-Hui Yu
  • Publication number: 20240170419
    Abstract: A package structure is provided. The package structure includes a die, an encapsulant and a RDL structure. The RDL structure is disposed on the die and the encapsulant. The RDL structure includes a first dielectric structure and a first redistribution layer. The first dielectric structure includes a first dielectric material layer and a second dielectric material layer on the first dielectric material layer. The first redistribution layer is embedded in the first dielectric structure and electrically connected to the die. The redistribution layer includes a first seed layer and a first conductive layer surrounded by the first seed layer. A topmost surface of the first seed layer and a topmost surface of the first conductive layer are substantially level with a top surface of the second dielectric material layer.
    Type: Application
    Filed: January 23, 2024
    Publication date: May 23, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chun-Hui Yu, Kuo-Chung Yee
  • Patent number: 11961789
    Abstract: A semiconductor package includes a chip, a redistribution structure, and first under-ball metallurgies patterns. The chip includes conductive posts exposed at an active surface. The redistribution structure is disposed on the active surface. The redistribution structure includes a first dielectric layer, a topmost metallization layer, and a second dielectric layer. The first dielectric layer includes first openings exposing the conductive posts of the chip. The topmost metallization layer is disposed over the first dielectric layer and is electrically connected to the conductive posts. The topmost metallization layer comprises first contact pads and routing traces connected to the first contact pads. The second dielectric layer is disposed on the topmost metallization layer and includes second openings exposing the first contact pads. The first under-ball metallurgies patterns are disposed on the first contact pads, extending on and contacting sidewalls and top surfaces of the first contact pads.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chun-Hui Yu, Kuo-Chung Yee
  • Publication number: 20240096760
    Abstract: A semiconductor package includes a chip, a redistribution structure, and first under- ball metallurgies patterns. The chip includes conductive posts exposed at an active surface. The redistribution structure is disposed on the active surface. The redistribution structure includes a first dielectric layer, a topmost metallization layer, and a second dielectric layer. The first dielectric layer includes first openings exposing the conductive posts of the chip. The topmost metallization layer is disposed over the first dielectric layer and is electrically connected to the conductive posts. The topmost metallization layer comprises first contact pads and routing traces connected to the first contact pads. The second dielectric layer is disposed on the topmost metallization layer and includes second openings exposing the first contact pads. The first under-ball metallurgies patterns are disposed on the first contact pads, extending on and contacting sidewalls and top surfaces of the first contact pads.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chun-Hui Yu, Kuo-Chung Yee
  • Publication number: 20240087986
    Abstract: A semiconductor device including a substrate, a semiconductor package, a thermal conductive bonding layer, and a lid is provided. The semiconductor package is disposed on the substrate. The thermal conductive bonding layer is disposed on the semiconductor package. The lid is attached to the thermal conductive bonding layer and covers the semiconductor package to prevent coolant from contacting the semiconductor package.
    Type: Application
    Filed: November 15, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chun-Hui Yu, Jeng-Nan Hung, Kuo-Chung Yee, Po-Fan Lin
  • Patent number: 11929345
    Abstract: In an embodiment, a device includes: a first device including: an integrated circuit device having a first connector; a first photosensitive adhesive layer on the integrated circuit device; and a first conductive layer on the first connector, the first photosensitive adhesive layer surrounding the first conductive layer; a second device including: an interposer having a second connector; a second photosensitive adhesive layer on the interposer, the second photosensitive adhesive layer physically connected to the first photosensitive adhesive layer; and a second conductive layer on the second connector, the second photosensitive adhesive layer surrounding the second conductive layer; and a conductive connector bonding the first and second conductive layers, the conductive connector surrounded by an air gap.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chun Hui Yu, Kuo-Chung Yee
  • Patent number: 11916028
    Abstract: A package structure and a method of forming the same are provided. The package structure includes a die, an encapsulant and a RDL structure, the encapsulant encapsulate sidewalls of the die. The RDL structure is disposed on the die and the encapsulant. The RDL structure includes a first dielectric structure and a first redistribution layer. The first dielectric structure includes a first dielectric material layer and a second dielectric material layer on the first dielectric material layer. The first redistribution layer is embedded in the first dielectric structure and electrically connected to the die, the redistribution layer comprises a first seed layer and a first conductive layer disposed on the first seed layer. A topmost surface of the first seed layer and a topmost surface of the first conductive layer are substantially level with a top surface of the second dielectric material layer.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chun-Hui Yu, Kuo-Chung Yee
  • Publication number: 20240047404
    Abstract: A structure including a first semiconductor die and a second semiconductor die is provided. The first semiconductor die includes a first bonding structure. The first bonding structure includes a first dielectric layer and first conductors embedded in the first dielectric layer. The second semiconductor die includes a second bonding structure. The second bonding structure includes a second dielectric layer and second conductors embedded in the second dielectric layer. The first dielectric layer is in contact with the second dielectric layer, and the first conductors are in contact with the second conductors. Thermal conductivity of the first dielectric layer and the second dielectric layer is greater than thermal conductivity of silicon dioxide.
    Type: Application
    Filed: October 18, 2023
    Publication date: February 8, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chun-Hui Yu, Jeng-Nan Hung, Kuo-Chung Yee, Po-Fan Lin
  • Patent number: 11888285
    Abstract: A low numerical aperture fiber output diode laser module, which having several independent diode lasers, and collimated and converged the light beam, for the coupling the light to the core optical fiber with a core diameter of 105 um and a numerical aperture of 0.12. Compared with general products with a numerical aperture of 0.22, the light output angle is reduced to 55%, and use a general blue laser diode for verification. Use an optical software for facilitating the design and optimization of the parameters of the optical lens module.
    Type: Grant
    Filed: July 27, 2021
    Date of Patent: January 30, 2024
    Assignee: Turning Point Lasers Corporation
    Inventors: Chi-Luen Wang, Hung-Sheng Lee, Tai-Ming Chang, Chun-Hui Yu, Yu-Ching Yeh, Sheng-Ping Lai, Shih-Wei Lin, Yuan-He Teng, Li-Chang Tsou, Szutsun Simon Ou
  • Patent number: 11854936
    Abstract: A semiconductor device including a substrate, a semiconductor package, a thermal conductive bonding layer, and a lid is provided. The semiconductor package is disposed on the substrate. The thermal conductive bonding layer is disposed on the semiconductor package. The lid is attached to the thermal conductive bonding layer and covers the semiconductor package to prevent coolant from contacting the semiconductor package.
    Type: Grant
    Filed: January 17, 2023
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chun-Hui Yu, Jeng-Nan Hung, Kuo-Chung Yee, Po-Fan Lin
  • Patent number: 11830844
    Abstract: A structure including a first semiconductor die and a second semiconductor die is provided. The first semiconductor die includes a first bonding structure. The first bonding structure includes a first dielectric layer and first conductors embedded in the first dielectric layer. The second semiconductor die includes a second bonding structure. The second bonding structure includes a second dielectric layer and second conductors embedded in the second dielectric layer. The first dielectric layer is in contact with the second dielectric layer, and the first conductors are in contact with the second conductors. Thermal conductivity of the first dielectric layer and the second dielectric layer is greater than thermal conductivity of silicon dioxide.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: November 28, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chun-Hui Yu, Jeng-Nan Hung, Kuo-Chung Yee, Po-Fan Lin
  • Patent number: 11756852
    Abstract: A semiconductor device including a substrate, a semiconductor package, a plurality of pillars and a lid is provided. The semiconductor package is disposed on the substrate and includes at least one semiconductor die. The plurality of pillars are disposed on the semiconductor package. The lid is disposed on the substrate and covers the semiconductor package and the plurality of pillars. The lid includes an inflow channel and an outflow channel to allow a coolant to flow into and out of a space between the substrate, the semiconductor package, the plurality of pillars and the lid. An inner surface of the lid, which faces and overlaps the plurality of pillars along a stacking direction of the semiconductor package and the lid, is a flat surface.
    Type: Grant
    Filed: April 14, 2022
    Date of Patent: September 12, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chun-Hui Yu, Jeng-Nan Hung, Kuo-Chung Yee, Po-Fan Lin
  • Publication number: 20230170280
    Abstract: A semiconductor device including a substrate, a semiconductor package, a thermal conductive bonding layer, and a lid is provided. The semiconductor package is disposed on the substrate. The thermal conductive bonding layer is disposed on the semiconductor package. The lid is attached to the thermal conductive bonding layer and covers the semiconductor package to prevent coolant from contacting the semiconductor package.
    Type: Application
    Filed: January 17, 2023
    Publication date: June 1, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chun-Hui Yu, Jeng-Nan Hung, Kuo-Chung Yee, Po-Fan Lin
  • Patent number: 11640954
    Abstract: A semiconductor package structure includes a plurality of first dies spaced from each other, a molding layer between the first dies, a second die over the plurality of first dies and the molding layer, and an adhesive layer between the plurality of first dies and the second die, and between the molding layer and the second die. A first interface between the adhesive layer and the molding layer and a second interface between the adhesive layer and the plurality of first dies are at different levels.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: May 2, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jeng-Nan Hung, Chun-Hui Yu, Kuo-Chung Yee, Yi-Da Tsai, Wei-Hung Lin, Ming-Da Cheng, Ching-Hua Hsieh
  • Patent number: 11574853
    Abstract: A semiconductor device including a substrate, a semiconductor package, a thermal conductive bonding layer, and a lid is provided. The semiconductor package is disposed on the substrate. The thermal conductive bonding layer is disposed on the semiconductor package. The lid is attached to the thermal conductive bonding layer and covers the semiconductor package to prevent coolant from contacting the semiconductor package.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: February 7, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chun-Hui Yu, Jeng-Nan Hung, Kuo-Chung Yee, Po-Fan Lin
  • Publication number: 20230037106
    Abstract: A low numerical aperture fiber output diode laser module, which having several independent diode lasers, and collimated and converged the light beam, for the coupling the light to the core optical fiber with a core diameter of 105 um and a numerical aperture of 0.12. Compared with general products with a numerical aperture of 0.22, the light output angle is reduced to 55%, and use a general blue laser diode for verification. Use an optical software for facilitating the design and optimization of the parameters of the optical lens module.
    Type: Application
    Filed: July 27, 2021
    Publication date: February 2, 2023
    Inventors: CHI-LUEN WANG, HUNG-SHENG LEE, TAI-MING CHANG, CHUN-HUI YU, YU-CHING YEH, SHENG PING LAI, SHIH-WEI LIN, YUAN-HE TENG, LI-CHANG TSOU, SZUTSUN SIMON OU
  • Patent number: 11545438
    Abstract: A semiconductor package includes a first interposer, a second interposer, a first die, a second die and at least one bridge structure. The first interposer and the second interposer are embedded by a first dielectric encapsulation. The first die is disposed over and electrically connected to the first interposer. The second die is disposed over and electrically connected to the second interposer. The at least one bridge structure is disposed between the first die and the second die.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: January 3, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yen Hsieh, Chun-Hui Yu, Ping-Kang Huang, Sao-Ling Chiu, Yi-Jhang Wang