Patents by Inventor Chun-hung Cheng

Chun-hung Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12232309
    Abstract: A capacitor includes cup-shaped lower electrodes disposed on a substrate, a capacitor dielectric layer conformally covering inner surfaces and outer surfaces of the cup-shaped lower electrodes, and a support layer disposed between outer surfaces of the cup-shaped lower electrodes to connect the cup-shaped lower electrodes. The capacitor further includes an annealed oxide layer, which is interposed between the inner surfaces of the cup-shaped lower electrodes and the capacitor dielectric layer, and is also interposed between a portion of the outer surfaces of the cup-shaped lower electrodes and the capacitor dielectric layer. A method for forming the capacitor is also provided.
    Type: Grant
    Filed: February 4, 2022
    Date of Patent: February 18, 2025
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Yu-Ping Hsiao, Cheol-Soo Park, Chun-Hung Cheng, Wei-Chieh Chuang, Wei-Chao Chou, Yen-Min Juan
  • Patent number: 12193345
    Abstract: A resistive random access memory (RRAM) structure includes a RRAM cell, spacers and a dielectric layer. The RRAM cell is disposed on a substrate. The spacers are disposed beside the RRAM cell, wherein widths of top surfaces of the spacers are larger than or equal to widths of bottom surfaces of the spacers. The dielectric layer blanketly covers the substrate and sandwiches the RRAM cell, wherein the spacers are located in the dielectric layer. A method for forming the resistive random access memory (RRAM) structure is also provided.
    Type: Grant
    Filed: November 6, 2023
    Date of Patent: January 7, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Jen Wang, Chun-Hung Cheng, Chuan-Fu Wang
  • Patent number: 12127488
    Abstract: A resistive random access memory structure includes a first inter-layer dielectric layer; a bottom electrode disposed in the first inter-layer dielectric layer; a capping layer disposed on the bottom electrode and on the first inter-layer dielectric layer; and a through hole disposed in the capping layer. The through hole partially exposes a top surface of the bottom electrode. A variable resistance layer is disposed within the through hole. A top electrode is disposed within the through hole and on the variable resistance layer. A second inter-layer dielectric layer covers the top electrode and the capping layer.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: October 22, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Jen Wang, Chun-Hung Cheng, Chuan-Fu Wang
  • Publication number: 20240334850
    Abstract: A resistive random access memory (RRAM) structure includes a RRAM cell, spacers and a dielectric layer. The RRAM cell is disposed on a substrate. The spacers are disposed beside the RRAM cell, wherein widths of top surfaces of the spacers are larger than or equal to widths of bottom surfaces of the spacers. The dielectric layer blanketly covers the substrate and sandwiches the RRAM cell, wherein the spacers are located in the dielectric layer. A method for forming the resistive random access memory (RRAM) structure is also provided.
    Type: Application
    Filed: June 13, 2024
    Publication date: October 3, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Jen Wang, Chun-Hung Cheng, Chuan-Fu Wang
  • Publication number: 20240312217
    Abstract: An object tracking system for use in traffic flow analytics and a traffic flow analytic method. The system comprises: an image processing module arranged to receiving a sequence of images capturing at least one object moving along a predetermined path in an area; an object detection module arranged to detect the at least one object including identifying a predetermined category of the detected object; and an object tracking module arranged to track the at least one object travelling from an entrance to an exit of the predetermined path based on coordinates of the object in the sequence of images being detected.
    Type: Application
    Filed: March 16, 2023
    Publication date: September 19, 2024
    Inventors: Chun Hung CHENG, Kwong Tim CHAN, Cheuk Wai KUNG
  • Publication number: 20240314526
    Abstract: The invention provides a drainage network monitoring system. The system comprises a sensing module for detecting one or more conditions at a location in the drainage network; a processing module for processing data received from the sensing module; a wireless communications module for communicating the processed data substantially in real-time to one or more wireless devices including a wireless notification device configured to issue notification information to users, wherein the wireless communications module utilizes a narrow bandwidth, low power wireless communications protocol to communicate processed data to the wireless notification device, and wherein the sensing module has a standalone power supply.
    Type: Application
    Filed: March 15, 2023
    Publication date: September 19, 2024
    Inventors: Chun Hung CHENG, Ho LAM, Shiu Kee LUK, Kwong Tim CHAN, Hoi Shun TAM
  • Publication number: 20240308465
    Abstract: A retrofit system for the monitoring of seatbelt status in mass transit vehicles is adapted for retrofitting in different existing vehicles and includes a plurality of non-contact position sensors each associated with the buckle and tongue of a seatbelt, and a seat pan upholstery module with a seat occupancy sensor fixed to its inner side. The sensor of the non-contact position sensors is adapted to be fixed to an external surface of the buckle housing. A monitoring unit is coupled to the non-contact position sensors and occupancy sensors and to a display of seatbelt status comprising an indication that, when each of the seats is occupied, whether the respective seatbelt is in the fastened positioned or a released position.
    Type: Application
    Filed: March 15, 2023
    Publication date: September 19, 2024
    Inventors: Chun Hung Cheng, Ho Lam, Shiu Kee Luk
  • Patent number: 12041863
    Abstract: A resistive random access memory (RRAM) structure includes a RRAM cell, spacers and a dielectric layer. The RRAM cell is disposed on a substrate. The spacers are disposed beside the RRAM cell, wherein widths of top surfaces of the spacers are larger than or equal to widths of bottom surfaces of the spacers. The dielectric layer blanketly covers the substrate and sandwiches the RRAM cell, wherein the spacers are located in the dielectric layer. A method for forming said resistive random access memory (RRAM) structure is also provided.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: July 16, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Jen Wang, Chun-Hung Cheng, Chuan-Fu Wang
  • Patent number: 12025770
    Abstract: A system (100) for monitoring stability of trees (10) in an area includes a server (101), one or more sensor modules (102, 202) being attached to each of the trees (10) in a network of trees, configured for obtaining tilt angle data pertaining to inclination of at least a portion of the tree (10), and relaying the tilt angle data to the server (101), a weather observing device (103, 203) connected to the server (101), for obtaining localized environmental variables representing a local weather condition in the area, and a monitoring platform (20) connected with the server (101), configured for storing and processing the data. The system is configured for monitoring, based on the data and the environmental variables, the tilt angle data of each of the trees (10), and identifying one or more abnormalities of one or more of the trees (10), and indicating through the monitoring platform (20) the one or more abnormalities.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: July 2, 2024
    Assignee: Logistics and Supply Chain MultiTech R&D Centre Limited
    Inventors: Kwong Yeung Simon Wong, Ho Lam, Wing Pong Ngai, Shiu Kee Luk, Chun Hung Cheng, Kwong Tim Chan
  • Patent number: 11997935
    Abstract: A resistive random-access memory (RRAM) device, including a bottom electrode, a high work function layer, a resistive material layer and a top electrode sequentially stacked on a substrate, wherein the resistive material layer includes a bottom part and a top part, first spacers covering sidewalls of the top part and the top electrode, and second spacers covering sidewalls of the bottom part, thereby constituting a RRAM cell.
    Type: Grant
    Filed: September 27, 2022
    Date of Patent: May 28, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shu-Hung Yu, Chun-Hung Cheng, Chuan-Fu Wang
  • Patent number: 11950521
    Abstract: A resistive random-access memory (RRAM) device includes a bottom electrode, a high work function layer, a resistive material layer, a top electrode and high work function spacers. The bottom electrode, the high work function layer, the resistive material layer and the top electrode are sequentially stacked on a substrate, wherein the resistive material layer includes a bottom part and a top part. The high work function spacers cover sidewalls of the bottom part, thereby constituting a RRAM cell. The present invention also provides a method of forming a RRAM device.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: April 2, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shu-Hung Yu, Chun-Hung Cheng, Chuan-Fu Wang
  • Publication number: 20240107901
    Abstract: Provided is a resistive random access memory (RRAM). The resistive random access memory includes a plurality of unit structures disposed on a substrate. Each of the unit structures includes a first electrode, and a first metal oxide layer. The first electrode is disposed on the substrate. The first metal oxide layer is disposed on the first electrode. In addition, the resistive random access memory includes a second electrode. The second electrode is disposed on the plurality of unit structures and connected to the plurality of unit structures.
    Type: Application
    Filed: December 5, 2023
    Publication date: March 28, 2024
    Applicant: United Microelectronics Corp.
    Inventors: Kai Jiun Chang, Chun-Hung Cheng, Chuan-Fu Wang
  • Publication number: 20240074338
    Abstract: A resistive random access memory (RRAM) structure includes a RRAM cell, spacers and a dielectric layer. The RRAM cell is disposed on a substrate. The spacers are disposed beside the RRAM cell, wherein widths of top surfaces of the spacers are larger than or equal to widths of bottom surfaces of the spacers. The dielectric layer blanketly covers the substrate and sandwiches the RRAM cell, wherein the spacers are located in the dielectric layer. A method for forming the resistive random access memory (RRAM) structure is also provided.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Jen Wang, Chun-Hung Cheng, Chuan-Fu Wang
  • Publication number: 20240074335
    Abstract: A RRAM device includes a bottom electrode, a resistive material layer, atop electrode, a hard mask and high work function sidewall parts. The bottom electrode, the resistive material layer, the top electrode and the hard mask are sequentially stacked on a substrate. The high work function sidewall parts cover sidewalls of the top electrode and sidewalls of the hard mask, thereby constituting a RRAM cell. A method of forming the RRAM device is also provided.
    Type: Application
    Filed: November 8, 2023
    Publication date: February 29, 2024
    Applicant: UNITED MICROELCTRONICS CORP.
    Inventors: Wen-Jen Wang, Chun-Hung Cheng, Chuan-Fu Wang
  • Publication number: 20240057487
    Abstract: An RRAM includes a bottom electrode, a resistive switching layer and a top electrode. The bottom electrode includes an inverted T-shaped profile. The resistive switching layer covers the bottom electrode. The top electrode covers the resistive switching layer. The inverted T-shaped profile includes a bottom element and a vertical element. The vertical element is disposed on the bottom element. The shape of the vertical element includes a rectangle or a trapezoid.
    Type: Application
    Filed: September 6, 2022
    Publication date: February 15, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Kai-Jiun Chang, Chun-Hung Cheng, Chuan-Fu Wang
  • Patent number: 11882773
    Abstract: Provided are a resistive random access memory (RRAM) and a manufacturing method thereof. The resistive random access memory includes multiple unit structures disposed on a substrate. Each of the unit structures includes a first electrode, a first metal oxide layer, and a spacer. The first electrode is disposed on the substrate. The first metal oxide layer is disposed on the first electrode. The spacer is disposed on sidewalls of the first electrode and the first metal oxide layer. In addition, the resistive random access memory includes a second metal oxide layer and a second electrode. The second metal oxide layer is disposed on the unit structures and is connected to the unit structures. The second electrode is disposed on the second metal oxide layer.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: January 23, 2024
    Assignee: United Microelectronics Corp.
    Inventors: Kai Jiun Chang, Chun-Hung Cheng, Chuan-Fu Wang
  • Patent number: 11871685
    Abstract: A RRAM device includes a bottom electrode, a resistive material layer, a high work function layer, a top electrode, a hard mask and high work function sidewall parts. The bottom electrode, the resistive material layer, the high work function layer, the top electrode and the hard mask are sequentially stacked on a substrate. The high work function sidewall parts cover sidewalls of the top electrode and sidewalls of the hard mask, thereby constituting a RRAM cell. A method of forming said RRAM device is also provided.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: January 9, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Jen Wang, Chun-Hung Cheng, Chuan-Fu Wang
  • Patent number: 11864473
    Abstract: Provided is a resistive random-access memory device, including a dielectric layer located on a substrate, a first electrode which is a column located on the dielectric layer, a second electrode covering a top surface and a sidewall of the first electrode, and a variable resistance layer sandwiched between the top surface of the first electrode and the second electrode and between the sidewall of the first electrode and the second electrode and located between the second electrode and the dielectric layer.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: January 2, 2024
    Assignee: United Microelectronics Corp.
    Inventors: Wen-Jen Wang, Chun-Hung Cheng, Chuan-Fu Wang
  • Publication number: 20230413698
    Abstract: A resistive random access memory structure includes a first inter-layer dielectric layer; a bottom electrode disposed in the first inter-layer dielectric layer; a capping layer disposed on the bottom electrode and on the first inter-layer dielectric layer; and a through hole disposed in the capping layer. The through hole partially exposes a top surface of the bottom electrode. A variable resistance layer is disposed within the through hole. A top electrode is disposed within the through hole and on the variable resistance layer. A second inter-layer dielectric layer covers the top electrode and the capping layer.
    Type: Application
    Filed: July 29, 2022
    Publication date: December 21, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Jen Wang, Chun-Hung Cheng, Chuan-Fu Wang
  • Publication number: 20230354724
    Abstract: Provided is a resistive memory structure and a manufacturing method thereof. The resistive memory structure includes a substrate, a dielectric layer, a resistive memory device, a hard mask layer, and a spacer. The dielectric layer is located on the substrate. The dielectric layer has an opening. The resistive memory device is located in the opening and has a protrusion outside the opening. The resistive memory device includes a first electrode, a variable resistance layer, and a second electrode. The variable resistance layer is located on the first electrode. The second electrode is located on the variable resistance layer. The hard mask layer covers a top surface of the variable resistance layer. The spacer covers a sidewall of the variable resistance layer in the protrusion.
    Type: Application
    Filed: May 23, 2022
    Publication date: November 2, 2023
    Applicant: United Microelectronics Corp.
    Inventors: Wen-Jen Wang, Chun-Hung Cheng, Chuan-Fu Wang