Abstract: A semiconductor device includes a substrate, a dielectric region, a first fin structure, a second fin structure, a plurality of conductive regions, a first conductive rail and a conductive structure. The dielectric region is situated on the substrate. The first fin structure protrudes from the substrate and the dielectric region. The second fin structure protrudes from the substrate and the dielectric region, and extends parallel to the first fin structure. The conductive regions are situated on the dielectric region. The first conductive rail is situated within the dielectric region, and electrically connected to a first conductive region of the plurality of conductive regions. Opposite sides of the first conductive rail face the first fin structure and the second fin structure, respectively. The conductive structure penetrates through the substrate and formed under the first conductive rail, and is electrically connected to the first conductive rail.

Abstract: A method for forming a non-planar semiconductor device includes: forming a fin structure protruding from a front side of a substrate of the non-planar semiconductor device; depositing a dielectric region on the front side of the substrate, the dielectric region including a conductive rail buried within the dielectric region and in parallel with the fin structure; etching the dielectric region to create a first opening in the dielectric region to expose the conductive rail; depositing a plurality of conductive regions on the dielectric region, one of the conductive regions contacting the conductive rail through the first opening; etching the substrate from a backside of the substrate to form a second opening to expose the conductive rail; and filling a first conductive material into the second opening to form a through-substrate via in the substrate.

Abstract: A method (of generating a layout diagram) includes: for a first cell which includes first and second active area patterns, a cell-boundary (CB) having first and second edge portions (EPs) substantially parallel to a vertical direction (VEPs), and first and second VEP-adjacent regions correspondingly adjacent the first and second VEPs: configuring the first VEP-adjacent region (VAR) to be a first active area (AA) continuous (AA-continuous) region in which the first active area pattern extends in a horizontal direction from an interior of the first cell to the first VEP; and configuring the second VAR to be a first AA-discontinuous region, the second active area pattern extending in the horizontal direction from the interior of the first cell towards the second VEP, and there being a first gap between a first end of the second active area pattern and the second VEP representing the first AA-discontinuous region.

Abstract: A method for forming a non-planar semiconductor device includes: forming a fin structure protruding from a front side of a substrate of the non-planar semiconductor device; depositing a dielectric region on the front side of the substrate, the dielectric region including a conductive rail buried within the dielectric region and in parallel with the fin structure; etching the dielectric region to create a first opening in the dielectric region to expose the conductive rail; depositing a plurality of conductive regions on the dielectric region, one of the conductive regions contacting the conductive rail through the first opening; etching the substrate from a backside of the substrate to form a second opening to expose the conductive rail; and filling a first conductive material into the second opening to form a through-substrate via in the substrate.

Abstract: A semiconductor device includes a substrate, a dielectric region, a plurality of conductive regions, a first conductive rail and a conductive structure. The dielectric region is situated on the substrate. The plurality of conductive regions are situated on the dielectric region. The first conductive rail is situated within the dielectric region, and is electrically connected to a first conductive region of the plurality of conductive regions. The conductive structure is arranged to penetrate through the substrate and formed under the first conductive rail. The conductive structure is electrically connected to the first conductive rail.

Abstract: A method (of generating a layout diagram) includes: for a first cell which includes first and second active area patterns, a cell-boundary (CB) having first and second edge portions (EPs) substantially parallel to a vertical direction (VEPs), and first and second VEP-adjacent regions correspondingly adjacent the first and second VEPs: configuring the first VEP-adjacent region (VAR) to be a first active area (AA) continuous (AA-continuous) region in which the first active area pattern extends in a horizontal direction from an interior of the first cell to the first VEP; and configuring the second VAR to be a first AA-discontinuous region, the second active area pattern extending in the horizontal direction from the interior of the first cell towards the second VEP, and there being a first gap between a first end of the second active area pattern and the second VEP representing the first AA-discontinuous region.

Abstract: A semiconductor device includes a substrate, a dielectric region, a plurality of conductive regions, a first conductive rail and a conductive structure. The dielectric region is situated on the substrate. The plurality of conductive regions are situated on the dielectric region. The first conductive rail is situated within the dielectric region, and is electrically connected to a first conductive region of the plurality of conductive regions. The conductive structure is arranged to penetrate through the substrate and formed under the first conductive rail. The conductive structure is electrically connected to the first conductive rail.

Abstract: A semiconductor device includes a substrate having source and drain regions, and a channel region arranged between the source and drain regions. The device further includes a gate structure over the substrate and adjacent to the channel region. The gate structure includes a gate stack, a spacer on sidewalls of the gate stack, and a conductor over the gate stack. The device further includes a first contact feature over the substrate and electrically connecting to at least one of the source and drain regions. A top surface of the first contact feature is lower than a top surface of the gate structure. The device further includes a first dielectric layer over the first contact feature. A top surface of the first dielectric layer is below or substantially co-planar with the top surface of the gate structure. The conductor at most partially overlaps in plan view with the first dielectric layer.

Abstract: A semiconductor device includes a substrate having source and drain regions, and a channel region arranged between the source and drain regions. The device further includes a gate structure over the substrate and adjacent to the channel region. The gate structure includes a gate stack, a spacer on sidewalls of the gate stack, and a conductor over the gate stack. The device further includes a first contact feature over the substrate and electrically connecting to at least one of the source and drain regions. A top surface of the first contact feature is lower than a top surface of the gate structure. The device further includes a first dielectric layer over the first contact feature. A top surface of the first dielectric layer is below or substantially co-planar with the top surface of the gate structure. The conductor at most partially overlaps in plan view with the first dielectric layer.

Abstract: Provided is a semiconductor device and methods of forming the same. The semiconductor device includes a substrate having source/drain regions and a channel region between the source/drain regions; a gate structure over the substrate and adjacent to the channel region; source/drain contacts over the source/drain regions and electrically connecting to the source/drain regions; and a contact protection layer over the source/drain contacts. The gate structure includes a gate stack and a spacer. A top surface of the source/drain contacts is lower than a top surface of the spacer, which is substantially co-planar with a top surface of the contact protection layer. The contact protection layer prevents accidental shorts between the gate stack and the source/drain regions when gate vias are formed over the gate stack. Therefore, gate vias may be formed over any portion of the gate stack, even in areas that overlap the channel region from a top view.

Abstract: Provided is a semiconductor device and methods of forming the same. The semiconductor device includes a substrate having source/drain regions and a channel region between the source/drain regions; a gate structure over the substrate and adjacent to the channel region; source/drain contacts over the source/drain regions and electrically connecting to the source/drain regions; and a contact protection layer over the source/drain contacts. The gate structure includes a gate stack and a spacer. A top surface of the source/drain contacts is lower than a top surface of the spacer, which is substantially co-planar with a top surface of the contact protection layer. The contact protection layer prevents accidental shorts between the gate stack and the source/drain regions when gate vias are formed over the gate stack. Therefore, gate vias may be formed over any portion of the gate stack, even in areas that overlap the channel region from a top view.

Abstract: A liquid crystal display mainly includes a first substrate and a second substrate processed for vertical alignment; a liquid crystal having a negative dielectric constant anisotropy and being sandwiched between the first and second substrates; an array of protrusions arranged in parallel to one another on the first substrate; and an array of slits provided on the pixel electrodes. The second substrate is provided with a plurality of gate lines, a plurality of data lines and a plurality of pixel electrodes. The pixel electrodes have first edges parallel to the gate lines and second edges parallel to the data lines. The protrusions have branches formed at positions facing the second edges of the pixel electrode in a manner that the angle included between the branches of the protrusions and the slits is kept at most 45 degrees.

Abstract: A liquid crystal display mainly includes a first substrate and a second substrate processed for vertical alignment; a liquid crystal having a negative dielectric constant anisotropy and being sandwiched between the first and second substrates; an array of protrusions arranged in parallel to one another on the first substrate; and an array of slits provided on the pixel electrodes. The second substrate is provided with a plurality of gate lines, a plurality of data lines and a plurality of pixel electrodes. The pixel electrodes have first edges parallel to the gate lines and second edges parallel to the data lines. The protrusions have branches formed at positions facing the second edges of the pixel electrode in a manner that the angle included between the branches of the protrusions and the slits is kept at most 45 degrees.