Patents by Inventor Chun-I Kuo

Chun-I Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240127767
    Abstract: A display device and a projector are provided. The display device includes a pixel light-emitting panel and multiple color conversion panels. The pixel light-emitting panel includes an N1 number of light-emitting pixel units distributed in an array, and the light-emitting pixel units are driven to emit light through a driver. A first color conversion panel includes an N2 number of first color pixels and an N3 number of first transparent pixels. The first color pixels and the first transparent pixels are disposed relative to the light-emitting pixel units. A second color conversion panel includes an N4 number of second color pixels and an N5 number of second transparent pixels. The second color pixels and the second transparent pixels are disposed relative to the light-emitting pixel units. The lights generated by at least part of the light-emitting pixel units sequentially pass through the first color pixels and the second transparent pixels to achieve the color conversion.
    Type: Application
    Filed: December 15, 2022
    Publication date: April 18, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Hui-Tang Shen, Wei-Hung Kuo, Kai-Ling Liang, Chun-I Wu, Yu-Hsiang Chang
  • Patent number: 11944412
    Abstract: A blood pressure detection device manufactured by a semiconductor process includes a substrate, a microelectromechanical element, a gas-pressure-sensing element, a driving-chip element, an encapsulation layer and a valve layer. The substrate includes inlet apertures. The microelectromechanical element and the gas-pressure-sensing element are stacked and integrally formed on the substrate. The encapsulation layer is encapsulated and positioned on the substrate. A flowing-channel space is formed above the microelectromechanical element and the gas-pressure-sensing element. The encapsulation layer includes an outlet aperture in communication with an airbag. The driving-chip element controls the microelectromechanical element, the gas-pressure-sensing element and valve units to transport gas.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: April 2, 2024
    Assignee: MICROJET TECHNOLOGY CO., LTD.
    Inventors: Hao-Jan Mou, Ying-Lun Chang, Ching-Sung Lin, Chi-Feng Huang, Yung-Lung Han, Chang-Yen Tsai, Wei-Ming Lee, Chun-Yi Kuo, Tsung-I Lin
  • Publication number: 20230261662
    Abstract: A Sigma Delta analog-to-digital converter (ADC) and a method for eliminating idle tones of the Sigma Delta ADC are provided. The Sigma Delta ADC includes a loop filter, a quantizer, an adder and a digital-to-analog converter (DAC). The loop filter performs filtering on a difference between an analog input signal and an analog feedback signal to generate a filtered signal. The quantizer is coupled to the loop filter, and generates a digital output signal according to the filtered signal. The adder is coupled to the quantizer, and adds a digital dithering signal to the digital output signal to generate a digital feedback signal. The DAC is coupled to the loop filter, and generates the analog feedback signal according to the digital feedback signal.
    Type: Application
    Filed: January 10, 2023
    Publication date: August 17, 2023
    Applicant: Realtek Semiconductor Corp.
    Inventors: Chun-I Kuo, Wen-Tze Chen, Yi-Jang Wu
  • Patent number: 11520366
    Abstract: The present application provides a voltage generation circuit and associated capacitor charging method and system. The voltage generation circuit is in a chip and is for generating a first output voltage and a second output voltage. The chip has a first output port and a second output port coupled to a first capacitor and a second capacitor respectively external to the chip. The voltage generation circuit includes a constant current type voltage generation unit and a regulator. When the voltage generation circuit operates in a first mode, the regulator is configured as a unit gain buffer to charge the first capacitor to the first output voltage; and when the voltage generation circuit operates in a second mode, the regulator is configured as a low-dropout regulator to charge the second capacitor to the second output voltage.
    Type: Grant
    Filed: October 28, 2021
    Date of Patent: December 6, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Chun-I Kuo
  • Patent number: 11455000
    Abstract: The present invention discloses a bias current generation circuit. An operation amplifier compares an input voltage having a zero-temperature coefficient and a feedback voltage to generate a driving voltage. An output transistor generates a bias current according to the driving voltage. A variable resistive circuit is electrically coupled to the output transistor through a feedback node to generate the feedback voltage according to the bias current and includes series-coupled resistors and switch transistors. Each of the resistors has a resistance having a positive temperature coefficient and includes a current input terminal and a current output terminal. Each of the switch transistors is electrically coupled between the current output terminal of one of the resistors and a ground terminal. One of the switch transistors turns on according to a control voltage variable according to the temperature variation to enable resistors to generate the resistance having a negative temperature coefficient.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: September 27, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chun-Ta Ho, Chun-I Kuo, Shawn Min
  • Publication number: 20220229456
    Abstract: The present application provides a voltage generation circuit and associated capacitor charging method and system. The voltage generation circuit is in a chip and is for generating a first output voltage and a second output voltage. The chip has a first output port and a second output port coupled to a first capacitor and a second capacitor respectively external to the chip. The voltage generation circuit includes a constant current type voltage generation unit and a regulator. When the voltage generation circuit operates in a first mode, the regulator is configured as a unit gain buffer to charge the first capacitor to the first output voltage; and when the voltage generation circuit operates in a second mode, the regulator is configured as a low-dropout regulator to charge the second capacitor to the second output voltage.
    Type: Application
    Filed: October 28, 2021
    Publication date: July 21, 2022
    Inventor: CHUN-I KUO
  • Patent number: 11251701
    Abstract: A high voltage tolerant output circuit includes a boost circuit, a first bias circuit, and a buffer circuit. The boost circuit includes a first transistor and an output node. A first terminal of the first transistor is coupled with the output node. The first bias circuit is coupled with the output node and a control terminal of the first transistor, and for dividing the output voltage of the output node. The first bias circuit is further configured to transmit the divided output voltage to the control terminal of the first transistor. The buffer circuit is coupled with a second terminal of the first transistor, and for setting a first voltage of the second terminal of the first transistor. The output voltage is positive correlated to the first voltage, and a maximum value of the output voltage is higher than or equal to a maximum value of the first voltage.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: February 15, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chun-I Kuo, Yi-Jang Wu, Chun-Ta Ho, Cheng-Yu Liu
  • Publication number: 20210265910
    Abstract: A high voltage tolerant output circuit includes a boost circuit, a first bias circuit, and a buffer circuit. The boost circuit includes a first transistor and an output node. A first terminal of the first transistor is coupled with the output node. The first bias circuit is coupled with the output node and a control terminal of the first transistor, and for dividing the output voltage of the output node. The first bias circuit is further configured to transmit the divided output voltage to the control terminal of the first transistor. The buffer circuit is coupled with a second terminal of the first transistor, and for setting a first voltage of the second terminal of the first transistor. The output voltage is positive correlated to the first voltage, and a maximum value of the output voltage is higher than or equal to a maximum value of the first voltage.
    Type: Application
    Filed: February 24, 2021
    Publication date: August 26, 2021
    Inventors: Chun-I Kuo, Yi-Jang Wu, Chun-Ta Ho, Cheng-Yu Liu
  • Publication number: 20210263548
    Abstract: The present invention discloses a bias current generation circuit. An operation amplifier compares an input voltage having a zero-temperature coefficient and a feedback voltage to generate a driving voltage. An output transistor generates a bias current according to the driving voltage. A variable resistive circuit is electrically coupled to the output transistor through a feedback node to generate the feedback voltage according to the bias current and includes series-coupled resistors and switch transistors. Each of the resistors has a resistance having a positive temperature coefficient and includes a current input terminal and a current output terminal. Each of the switch transistors is electrically coupled between the current output terminal of one of the resistors and a ground terminal. One of the switch transistors turns on according to a control voltage variable according to the temperature variation to enable resistors to generate the resistance having a negative temperature coefficient.
    Type: Application
    Filed: February 23, 2021
    Publication date: August 26, 2021
    Inventors: CHUN-TA HO, CHUN-I KUO, SHAWN MIN
  • Patent number: 7751908
    Abstract: A thermal process system. The thermal process system comprises a thermal processor, a metrology tool, and a controller. The thermal processor performs a thermal process as defined by a heating model to form a film on a wafer surface. The metrology tool, interfaced with the thermal processor, inspects thickness of the film. The controller, coupled with the thermal processor and the metrology tool, generates the heating model of the thermal processor and calibrates the heating model according to a preset slope coefficient matrix and the measured thickness.
    Type: Grant
    Filed: December 2, 2004
    Date of Patent: July 6, 2010
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yung-Chih Chang, Cheng-I Sun, Chun-I Kuo, Fu-Kun Yeh, Hsueh-Chi Shen
  • Publication number: 20060122728
    Abstract: A thermal process system. The thermal process system comprises a thermal processor, a metrology tool, and a controller. The thermal processor performs a thermal process as defined by a heating model to form a film on a wafer surface. The metrology tool, interfaced with the thermal processor, inspects thickness of the film. The controller, coupled with the thermal processor and the metrology tool, generates the heating model of the thermal processor and calibrates the heating model according to a preset slope coefficient matrix and the measured thickness.
    Type: Application
    Filed: December 2, 2004
    Publication date: June 8, 2006
    Inventors: Yung-Chih Chang, Cheng-I Sun, Chun-I Kuo, Fu-Kun Yeh, Hsueh-Chi Shen