Patents by Inventor Chun-Jiun Dai
Chun-Jiun Dai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11574098Abstract: A system includes a net-identifying module and a false path-eliminating module. The net-identifying module is configured to receive first and second electronic lists associated with a circuit unit, to identify a net of the circuit unit based on the first electronic list, and to provide a net information output that includes information associated with the net. The false path-eliminating module is coupled to the net-identifying module and is configured to select, in the second electronic list, a path of the circuit unit that does not traverse through the net and provide a path information output that includes information associated with the path.Type: GrantFiled: June 25, 2021Date of Patent: February 7, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chun-Jiun Dai, Hung-Jen Liao, Wei-Min Chan, Yen-Huei Chen
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Publication number: 20210319160Abstract: A system includes a net-identifying module and a false path-eliminating module. The net-identifying module is configured to receive first and second electronic lists associated with a circuit unit, to identify a net of the circuit unit based on the first electronic list, and to provide a net information output that includes information associated with the net. The false path-eliminating module is coupled to the net-identifying module and is configured to select, in the second electronic list, a path of the circuit unit that does not traverse through the net and provide a path information output that includes information associated with the path.Type: ApplicationFiled: June 25, 2021Publication date: October 14, 2021Inventors: Chun-Jiun Dai, Hung-Jen Liao, Wei-Min Chan, Yen-Huei Chen
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Patent number: 11048840Abstract: A system includes a net-identifying module and a false path-eliminating module. The net-identifying module is configured to receive first and second electronic lists associated with a circuit unit, to identify a net of the circuit unit based on the first electronic list, and to provide a net information output that includes information associated with the net. The false path-eliminating module is coupled to the net-identifying module and is configured to select, in the second electronic list, a path of the circuit unit that does not traverse through the net and provide a path information output that includes information associated with the path.Type: GrantFiled: April 15, 2019Date of Patent: June 29, 2021Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chun-Jiun Dai, Hung-Jen Liao, Wei-Min Chan, Yen-Huei Chen
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Publication number: 20200020390Abstract: A static random access memory (SRAM) circuit can group the column bit lines in a memory array into subsets of bit lines, and a y-address signal input is provided for each subset of bit lines. Additionally or alternatively, each row in the array of memory cells is operably connected to multiple word lines.Type: ApplicationFiled: July 10, 2019Publication date: January 16, 2020Inventors: Hidehiro Fujiwara, Chun-Jiun Dai, Chih-Yu Lin, Yen-Huei Chen, Hiroki Noguchi
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Publication number: 20190236241Abstract: A system includes a net-identifying module and a false path-eliminating module. The net-identifying module is configured to receive first and second electronic lists associated with a circuit unit, to identify a net of the circuit unit based on the first electronic list, and to provide a net information output that includes information associated with the net. The false path-eliminating module is coupled to the net-identifying module and is configured to select, in the second electronic list, a path of the circuit unit that does not traverse through the net and provide a path information output that includes information associated with the path.Type: ApplicationFiled: April 15, 2019Publication date: August 1, 2019Inventors: Chun-Jiun Dai, Hung-Jen Liao, Wei-Min Chan, Yen-Huei Chen
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Patent number: 10275561Abstract: A system includes a net-identifying module and a false path-eliminating module. The net-identifying module is configured to receive first and second electronic lists associated with a circuit unit, to identify a net of the circuit unit based on the first electronic list, and to provide a net information output that includes information associated with the net. The false path-eliminating module is coupled to the net-identifying module and is configured to eliminate a false path of the circuit unit in the second electronic list based on the net information output.Type: GrantFiled: December 2, 2016Date of Patent: April 30, 2019Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chun-Jiun Dai, Hung-Jen Liao, Wei-Min Chan, Yen-Huei Chen
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Patent number: 10268787Abstract: A hybrid timing analysis method includes: receiving a pre-layout netlist, a post-layout netlist and a configuration file associated with an integrated circuit design; generating a first measurement script and an input stimulus waveform file according to the configuration file; performing a first dynamic timing analysis upon the pre-layout netlist by using the first measurement script and the input stimulus waveform file to generate a pre-layout simulation result; identifying at least one data path and at least one clock path according to the pre-layout simulation result; generating a second measurement script according to the at least on data path and at least one clock path; and performing a second dynamic timing analysis upon the post-layout netlist by using the second measurement script and the input stimulus waveform file to generate a first post-layout simulation result. Associated system and non-transitory computer readable medium are also provided.Type: GrantFiled: July 17, 2017Date of Patent: April 23, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chun-Jiun Dai, Wei Min Chan, Yen-Huei Chen, Hung-Jen Liao, Jonathan Tsung-Yung Chang
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Publication number: 20190018917Abstract: The present disclosure provides a hybrid timing analysis method. The method includes: receiving a pre-layout netlist, a post-layout netlist and a configuration file associated with an integrated circuit design; generating a first measurement script and an input stimulus waveform file according to the configuration file; performing a first dynamic timing analysis upon the pre-layout netlist by using the first measurement script and the input stimulus waveform file to generate a pre-layout simulation result; identifying at least one data path and at least one clock path according to the pre-layout simulation result; generating a second measurement script according to the at least on data path and at least one clock path; and performing a second dynamic timing analysis upon the post-layout netlist by using the second measurement script and the input stimulus waveform file to generate a first post-layout simulation result. Associated system and non-transitory computer readable medium are also provided.Type: ApplicationFiled: July 17, 2017Publication date: January 17, 2019Inventors: CHUN-JIUN DAI, WEI MIN CHAN, YEN-HUEI CHEN, HUNG-JEN LIAO, JONATHAN TSUNG-YUNG CHANG
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Patent number: 10001801Abstract: A voltage providing circuit includes a first circuit configured to receive a first input signal and a second input signal and to generate an output signal. The first circuit includes a first transistor configured to switchably couple the second input signal to a first node responsive to the first input signal, a second transistor having a gate terminal coupled with the first node, and a third transistor having a source terminal coupled with a source terminal of the second transistor. The third transistor is configured to set a reference voltage value at the source terminal of the second transistor if the first input signal indicates that the second input signal is pulled from a first voltage value toward a second voltage value and if the second input signal reaches a predetermined voltage value. A second circuit is configured to receive the output signal and to generate an output voltage.Type: GrantFiled: July 22, 2015Date of Patent: June 19, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: I-Han Huang, Chia-En Huang, Chih-Chieh Chiu, Fu-An Wu, Chun-Jiun Dai, Hong-Chen Cheng, Jung-Ping Yang, Cheng Hung Lee
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Publication number: 20170344696Abstract: A system includes a net-identifying module and a false path-eliminating module. The net-identifying module is configured to receive first and second electronic lists associated with a circuit unit, to identify a net of the circuit unit based on the first electronic list, and to provide a net information output that includes information associated with the net. The false path-eliminating module is coupled to the net-identifying module and is configured to eliminate a false path of the circuit unit in the second electronic list based on the net information output.Type: ApplicationFiled: December 2, 2016Publication date: November 30, 2017Inventors: Chun-Jiun Dai, Hung-Jen Liao, Wei-Min Chan, Yen-Huei Chen
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Patent number: 9275181Abstract: One or more techniques or systems for designing a cell are provided. The cell generally includes one or more transistors, such as a pass gate transistor, a pull up transistor, or a pull down transistor, respectively associated one or more gate to gate distances. In some embodiments, a second gate to gate distance is selected based on a first gate to gate distance. For example, the first gate to gate distance and the second gate to gate distance are associated with a first transistor. In another example, the first gate to gate distance is associated with a first transistor and the second gate to gate distance is associated with a second transistor. In this manner, a cell design is provided to improve a static noise margin (SNM) or a write margin (WM) for the cell, for example.Type: GrantFiled: September 21, 2012Date of Patent: March 1, 2016Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chia-En Huang, Yi-Hung Tsai, Chih-Chieh Chiu, Hsiao-Lan Yang, I-Han Huang, Chun-Jiun Dai, Fu-An Wu, Hong-Chen Cheng, Jung-Ping Yang, Cheng Hung Lee
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Publication number: 20150323951Abstract: A voltage providing circuit includes a first circuit configured to receive a first input signal and a second input signal and to generate an output signal. The first circuit includes a first transistor configured to switchably couple the second input signal to a first node responsive to the first input signal, a second transistor having a gate terminal coupled with the first node, and a third transistor having a source terminal coupled with a source terminal of the second transistor. The third transistor is configured to set a reference voltage value at the source terminal of the second transistor if the first input signal indicates that the second input signal is pulled from a first voltage value toward a second voltage value and if the second input signal reaches a predetermined voltage value. A second circuit is configured to receive the output signal and to generate an output voltage.Type: ApplicationFiled: July 22, 2015Publication date: November 12, 2015Inventors: I-Han HUANG, Chia-En HUANG, Chih-Chieh CHIU, Fu-An WU, Chun-Jiun DAI, Hong-Chen CHENG, Jung-Ping YANG, Cheng Hung LEE
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Patent number: 9104214Abstract: A voltage providing circuit includes a first circuit, a second circuit coupled with the first circuit, and a third circuit coupled with the second circuit. The first circuit is configured to receive a first input signal and to generate a first output signal. The second circuit is configured to receive the first input signal and the first output signal as inputs and to generate a second output signal. The third circuit is configured to receive the second output signal and to generate an output voltage.Type: GrantFiled: February 27, 2013Date of Patent: August 11, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: I-Han Huang, Chia-En Huang, Chih-Chieh Chiu, Fu-An Wu, Chun-Jiun Dai, Hong-Chen Cheng, Jung-Ping Yang, Cheng Hung Lee