Abstract: A sample analyzing method and a sample preparing method are provided. The sample analyzing method includes a sample preparing step, a placing step, and an analyzing step. The sample preparing step includes an obtaining step implemented by obtaining an identification information; and a marking and placing step implemented by placing a sample carrying component having a sample disposed thereon into a marking equipment, allowing the marking equipment to utilize the identification information to form an identification structure on the sample carrying component, and placing the sample carrying component into one of the accommodating slots according to the identification information. The placing step is implemented by taking out the sample carrying component from one of the accommodating slots and placing the sample carrying component into an electron microscope equipment. The analyzing step is implemented by utilizing the electron microscope equipment to photograph the sample to generate an analyzation image.

Abstract: A sense circuit includes memory cell characterization circuitry, storage circuitry, switching circuitry, and bit line biasing circuitry. The sense circuit is configured to perform a sense operation to sense a characterization of a memory cell. During a pre-charge phase, the memory cell characterization circuitry and the bit line biasing circuitry set differential voltages in the storage circuitry to levels dependent on input offset voltages according to certain polarities. The storage circuitry maintains the differential voltages during the sense phase, allowing the memory cell characterization circuitry to cancel output the input offset voltages when generating output voltages used to identify a characterization of the memory cell. The memory cell characterization circuitry also generates its output voltage based on a reference current through a reference bit line.

Abstract: A sense circuit includes memory cell characterization circuitry, storage circuitry, switching circuitry, and bit line biasing circuitry. The sense circuit is configured to perform a sense operation to sense a characterization of a memory cell. During a pre-charge phase, the memory cell characterization circuitry and the bit line biasing circuitry set differential voltages in the storage circuitry to levels dependent on input offset voltages according to certain polarities. The storage circuitry maintains the differential voltages during the sense phase, allowing the memory cell characterization circuitry to cancel output the input offset voltages when generating output voltages used to identify a characterization of the memory cell. The memory cell characterization circuitry also generates its output voltage based on a reference current through a reference bit line.