Patents by Inventor Chun-Jui Huang

Chun-Jui Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12315981
    Abstract: A transmission line device includes a daisy chain structure composed of at least three daisy chain units arranged periodically and continuously. Each of the daisy chain units includes first, second and third conductive lines, and first and second conductive pillars. The first and second conductive lines at a first layer extend along a first direction and are discontinuously arranged. The third conductive line at a second layer extends along the first direction and is substantially parallel to the first and second conductive lines. The first conductive pillar extends in a second direction. The second direction is different from the first direction. A first part of the first conductive pillar is connected to the first and third conductive lines. The second conductive pillar extends in the second direction. A first part of the second conductive pillar is connected to the second and third conductive lines.
    Type: Grant
    Filed: November 25, 2022
    Date of Patent: May 27, 2025
    Assignees: UNIMICRON TECHNOLOGY CORP., NATIONAL TAIWAN UNIVERISTY
    Inventors: Yu-Kuang Wang, Ruey-Beei Wu, Ching-Sheng Chen, Chun-Jui Huang, Wei-Yu Liao, Chi-Min Chang
  • Publication number: 20240397621
    Abstract: A circuit board device includes a transition region that includes a first conductive layer at a first level, a second conductive layer at a second level, and conductive vias. The first conductive layer includes a pad connected to the solderless connector, a transmission line, and a first reference layer. The transmission line includes first and second segments. A second width of the second segment is the same as or less than a first width of the first segment. The first reference layer has a first anti-pad region for the pad and the transmission line disposed therein. In a plan view, the first anti-pad region surrounding the pad is completely located within a second anti-pad region of a second reference layer of the second conductive layer. The conductive vias are disposed between the first and second conductive layers and surround the pad.
    Type: Application
    Filed: June 30, 2023
    Publication date: November 28, 2024
    Applicants: UNIMICRON TECHNOLOGY CORP., National Taiwan University
    Inventors: Chin-Hsun WANG, Ruey-Beei WU, Chun-Jui HUANG, Wei-Yu LIAO, Ching-Sheng CHEN, Chi-Min CHANG
  • Patent number: 12133323
    Abstract: A transmission device for suppressing the glass-fiber effect includes a circuit board and a transmission line. The circuit board includes a plurality of glass fibers, so as to define a fiber pitch. The transmission line is disposed on the circuit board. The transmission line includes a plurality of non-parallel segments. Each of the non-parallel segments of the transmission line has an offset distance with respect to a reference line. The offset distance is longer than or equal to a half of the fiber pitch.
    Type: Grant
    Filed: November 23, 2022
    Date of Patent: October 29, 2024
    Assignees: UNIMICRON TECHNOLOGY CORP., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chin-Hsun Wang, Ruey-Beei Wu, Ching-Sheng Chen, Chun-Jui Huang, Wei-Yu Liao, Chi-Min Chang
  • Publication number: 20240128626
    Abstract: A transmission device includes a daisy chain structure composed of at least three daisy chain units arranged periodically and continuously. Each of the daisy chain units includes first, second and third conductive lines, and first and second conductive pillars. The first and second conductive lines at a first layer extend along a first direction and are discontinuously arranged. The third conductive line at a second layer extends along the first direction and is substantially parallel to the first and second conductive lines. The first conductive pillar extends in a second direction. The second direction is different from the first direction. A first part of the first conductive pillar is connected to the first and third conductive lines. The second conductive pillar extends in the second direction. A first part of the second conductive pillar is connected to the second and third conductive lines.
    Type: Application
    Filed: November 25, 2022
    Publication date: April 18, 2024
    Applicants: UNIMICRON TECHNOLOGY CORP., National Taiwan University
    Inventors: Yu-Kuang WANG, Ruey-Beei Wu, Ching-Sheng Chen, Chun-Jui Huang, Wei-Yu Liao, Chi-Min Chang
  • Patent number: 11942367
    Abstract: A semiconductor device such as a fin field effect transistor and its method of manufacture are provided. In some embodiments gate spacers are formed over a semiconductor fin, and a first gate stack is formed over the fin. A first sacrificial material with a large selectivity to the gate spacers is formed over the gate stack, and a second sacrificial material with a large selectivity is formed over a source/drain contact plug. Etching processes are utilized to form openings through the first sacrificial material and through the second sacrificial material, and the openings are filled with a conductive material.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chan Syun David Yang, Li-Te Lin, Chun-Jui Huang
  • Publication number: 20230386921
    Abstract: A semiconductor device such as a fin field effect transistor and its method of manufacture are provided. In some embodiments gate spacers are formed over a semiconductor fin, and a first gate stack is formed over the fin. A first sacrificial material with a large selectivity to the gate spacers is formed over the gate stack, and a second sacrificial material with a large selectivity is formed over a source/drain contact plug. Etching processes are utilized to form openings through the first sacrificial material and through the second sacrificial material, and the openings are filled with a conductive material.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Inventors: Chan Syun David Yang, Li-Te Lin, Chun-Jui Huang
  • Publication number: 20230197515
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate structure formed over a substrate, and the gate structure includes a gate dielectric layer and a gate electrode layer. The semiconductor device structure includes an insulating capping layer formed over the gate electrode layer, and the insulating capping layer covers a top surface of the gate dielectric layer. The semiconductor device structure also includes a conductive via structure formed through the insulating capping layer, and a portion of the conductive via structure is lower than a top surface of the gate dielectric layer.
    Type: Application
    Filed: February 13, 2023
    Publication date: June 22, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Jui HUANG, Li-Te LIN, Pinyen LIN
  • Patent number: 11581222
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate stack and a source/drain contact structure formed over a substrate. A first gate spacer is separated the gate stack from the source/drain contact structure and extends above top surfaces of the gate stack and the source/drain contact structure. An insulating capping layer covers the top surface of the gate stack and extends on the top surface of the first gate spacer. A conductive via structure partially covers the top surface of the insulating capping layer and the top surface of the source/drain contact structure. A first insulating layer surrounds the conductive via structure and partially covers the top surface of the source/drain contact structure.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: February 14, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Jui Huang, Li-Te Lin, Pinyen Lin
  • Publication number: 20210111071
    Abstract: A semiconductor device such as a fin field effect transistor and its method of manufacture are provided. In some embodiments gate spacers are formed over a semiconductor fin, and a first gate stack is formed over the fin. A first sacrificial material with a large selectivity to the gate spacers is formed over the gate stack, and a second sacrificial material with a large selectivity is formed over a source/drain contact plug. Etching processes are utilized to form openings through the first sacrificial material and through the second sacrificial material, and the openings are filled with a conductive material.
    Type: Application
    Filed: December 7, 2020
    Publication date: April 15, 2021
    Inventors: Chan Syun David Yang, Li-Te Lin, Chun-Jui Huang
  • Publication number: 20200411378
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate stack and a source/drain contact structure formed over a substrate. A first gate spacer is separated the gate stack from the source/drain contact structure and extends above top surfaces of the gate stack and the source/drain contact structure. An insulating capping layer covers the top surface of the gate stack and extends on the top surface of the first gate spacer. A conductive via structure partially covers the top surface of the insulating capping layer and the top surface of the source/drain contact structure. A first insulating layer surrounds the conductive via structure and partially covers the top surface of the source/drain contact structure.
    Type: Application
    Filed: September 11, 2020
    Publication date: December 31, 2020
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Jui HUANG, Li-Te LIN, Pinyen LIN
  • Patent number: 10861745
    Abstract: A semiconductor device such as a fin field effect transistor and its method of manufacture are provided. In some embodiments gate spacers are formed over a semiconductor fin, and a first gate stack is formed over the fin. A first sacrificial material with a large selectivity to the gate spacers is formed over the gate stack, and a second sacrificial material with a large selectivity is formed over a source/drain contact plug. Etching processes are utilized to form openings through the first sacrificial material and through the second sacrificial material, and the openings are filled with a conductive material.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chan Syun David Yang, Li-Te Lin, Chun-Jui Huang
  • Patent number: 10777455
    Abstract: A method for forming a semiconductor device structure is provided. A gate structure and a source/drain contact structure are formed over a substrate. The gate structure is covered with a capping layer. The capping layer and the source/drain contact structure are successively covered with a first insulating layer and a second insulating layer. A via opening is formed in the second insulating layer to expose the first insulating layer above the source/drain contact structure. The exposed first insulating layer is recessed using a first etching gas mixture including an oxygen gas, to leave a portion of the first insulating layer. The left portion of the first insulating layer using a second etching gas mixture including a hydrogen gas, to expose the source/drain contact structure. A conductive material is formed in the via opening to electrically connect the source/drain contact structure.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: September 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Jui Huang, Li-Te Lin, Pinyen Lin
  • Publication number: 20200243385
    Abstract: A method for forming a semiconductor device structure is provided. A gate structure and a source/drain contact structure are formed over a substrate. The gate structure is covered with a capping layer. The capping layer and the source/drain contact structure are successively covered with a first insulating layer and a second insulating layer. A via opening is formed in the second insulating layer to expose the first insulating layer above the source/drain contact structure. The exposed first insulating layer is recessed using a first etching gas mixture including an oxygen gas, to leave a portion of the first insulating layer. The left portion of the first insulating layer using a second etching gas mixture including a hydrogen gas, to expose the source/drain contact structure. A conductive material is formed in the via opening to electrically connect the source/drain contact structure.
    Type: Application
    Filed: January 29, 2019
    Publication date: July 30, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Jui HUANG, Li-Te LIN, Pinyen LIN
  • Publication number: 20190164829
    Abstract: A semiconductor device such as a fin field effect transistor and its method of manufacture are provided. In some embodiments gate spacers are formed over a semiconductor fin, and a first gate stack is formed over the fin. A first sacrificial material with a large selectivity to the gate spacers is formed over the gate stack, and a second sacrificial material with a large selectivity is formed over a source/drain contact plug. Etching processes are utilized to form openings through the first sacrificial material and through the second sacrificial material, and the openings are filled with a conductive material.
    Type: Application
    Filed: February 19, 2018
    Publication date: May 30, 2019
    Inventors: Chan Syun David Yang, Li-Te Lin, Chun-Jui Huang