Patents by Inventor Chun-Jun ZHUANG
Chun-Jun ZHUANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12142576Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first passivation layer, a first metal layer and a first semiconductor die. The first metal layer is embedded in the first passivation layer. The first metal layer defines a first through-hole. The first semiconductor die is disposed on the first passivation layer.Type: GrantFiled: March 14, 2023Date of Patent: November 12, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Hsu-Nan Fang, Chun-Jun Zhuang
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Publication number: 20230223352Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first passivation layer, a first metal layer and a first semiconductor die. The first metal layer is embedded in the first passivation layer. The first metal layer defines a first through-hole. The first semiconductor die is disposed on the first passivation layer.Type: ApplicationFiled: March 14, 2023Publication date: July 13, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Hsu-Nan FANG, Chun-Jun ZHUANG
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Patent number: 11605597Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first passivation layer, a first metal layer and a first semiconductor die. The first metal layer is embedded in the first passivation layer. The first metal layer defines a first through-hole. The first semiconductor die is disposed on the first passivation layer.Type: GrantFiled: April 17, 2020Date of Patent: March 14, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Hsu-Nan Fang, Chun-Jun Zhuang
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Publication number: 20220367369Abstract: A semiconductor package structure includes at least one first semiconductor die, at least one second semiconductor die and an encapsulant. The first semiconductor die has a first surface and includes a plurality of first pillar structures disposed adjacent to the first surface. The second semiconductor die is electrically connected to the first semiconductor die. The encapsulant covers the first semiconductor die and the second semiconductor die. A lower surface of the encapsulant is substantially coplanar with an end surface of each of the first pillar structures and a surface of the second semiconductor die.Type: ApplicationFiled: August 2, 2022Publication date: November 17, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Hsu-Nan FANG, Chun-Jun ZHUANG
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Patent number: 11404380Abstract: A semiconductor package structure includes at least one first semiconductor die, at least one second semiconductor die and an encapsulant. The first semiconductor die has a first surface and includes a plurality of first pillar structures disposed adjacent to the first surface. The second semiconductor die is electrically connected to the first semiconductor die. The encapsulant covers the first semiconductor die and the second semiconductor die. A lower surface of the encapsulant is substantially coplanar with an end surface of each of the first pillar structures and a surface of the second semiconductor die.Type: GrantFiled: December 19, 2019Date of Patent: August 2, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Hsu-Nan Fang, Chun-Jun Zhuang
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Patent number: 11257788Abstract: A semiconductor device package includes a first electronic component, a plurality of first conductive traces, a second electronic component, a plurality of second conductive traces and a plurality of first conductive structures. The first electronic component has a first active surface. The first conductive traces are disposed on and electrically connected to the first active surface. The second electronic component is stacked on the first electronic component. The second electronic component has an inactive surface facing the first active surface, a second active surface opposite the inactive surface, and at least one lateral surface connecting the second active surface and the inactive surface. The second conductive traces are electrically connected to the second active surface, and extending from the second active surface to the lateral surface. The first conductive structures are electrically connecting the second conductive traces to the first conductive traces, respectively.Type: GrantFiled: September 24, 2019Date of Patent: February 22, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Hsu-Nan Fang, Chun-Jun Zhuang
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Patent number: 11211319Abstract: A device structure includes a first electronic structure and a plurality of first electric contacts. The first electronic structure has a surface and a center. The first electric contacts are exposed from the surface. The first electric contacts are spaced by a pitch that increases with increasing distance from the center.Type: GrantFiled: November 21, 2019Date of Patent: December 28, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Hsu-Nan Fang, Chun-Jun Zhuang, Chen Yuan Weng
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Publication number: 20210327819Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first passivation layer, a first metal layer and a first semiconductor die. The first metal layer is embedded in the first passivation layer. The first metal layer defines a first through-hole. The first semiconductor die is disposed on the first passivation layer.Type: ApplicationFiled: April 17, 2020Publication date: October 21, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Hsu-Nan FANG, Chun-Jun ZHUANG
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Patent number: 11139252Abstract: A semiconductor package includes a semiconductor die, a plurality of conductive bumps, a shielding layer, an encapsulant and a redistribution layer. The semiconductor die has an active surface, a backside surface and a lateral surface. The conductive bumps are disposed on the active surface of the semiconductor die. The shielding layer is disposed on the lateral surface of the semiconductor die. The encapsulant covers the shielding layer, and has a first surface and a second surface opposite to the first surface. The redistribution layer is disposed on the first surface of the encapsulant and electrically connected to the semiconductor die through the conductive bumps. The shielding layer is electrically connected to the redistribution layer.Type: GrantFiled: February 26, 2020Date of Patent: October 5, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Hsu-Nan Fang, Chun-Jun Zhuang, Yung I. Yeh
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Publication number: 20210193578Abstract: A semiconductor package structure includes at least one first semiconductor die, at least one second semiconductor die and an encapsulant. The first semiconductor die has a first surface and includes a plurality of first pillar structures disposed adjacent to the first surface. The second semiconductor die is electrically connected to the first semiconductor die. The encapsulant covers the first semiconductor die and the second semiconductor die. A lower surface of the encapsulant is substantially coplanar with an end surface of each of the first pillar structures and a surface of the second semiconductor die.Type: ApplicationFiled: December 19, 2019Publication date: June 24, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Hsu-Nan FANG, Chun-Jun ZHUANG
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Publication number: 20210159156Abstract: A device structure includes a first electronic structure and a plurality of first electric contacts. The first electronic structure has a surface and a center. The first electric contacts are exposed from the surface. The first electric contacts are spaced by a pitch that increases with increasing distance from the center.Type: ApplicationFiled: November 21, 2019Publication date: May 27, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Hsu-Nan FANG, Chun-Jun ZHUANG, Chen Yuan WENG
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Publication number: 20210091042Abstract: A semiconductor device package includes a first electronic component, a plurality of first conductive traces, a second electronic component, a plurality of second conductive traces and a plurality of first conductive structures. The first electronic component has a first active surface. The first conductive traces are disposed on and electrically connected to the first active surface. The second electronic component is stacked on the first electronic component. The second electronic component has an inactive surface facing the first active surface, a second active surface opposite the inactive surface, and at least one lateral surface connecting the second active surface and the inactive surface. The second conductive traces are electrically connected to the second active surface, and extending from the second active surface to the lateral surface. The first conductive structures are electrically connecting the second conductive traces to the first conductive traces, respectively.Type: ApplicationFiled: September 24, 2019Publication date: March 25, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Hsu-Nan FANG, Chun-Jun ZHUANG
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Patent number: 10886223Abstract: A semiconductor package includes a redistribution layer (RDL) structure, a first die, a molding compound and an interconnect structure. The first die is disposed on the RDL structure. The molding compound is disposed on the RDL structure. The interconnect structure electrically connects the first die to the RDL structure.Type: GrantFiled: June 3, 2019Date of Patent: January 5, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chun-Jun Zhuang, Hsu-Nan Fang
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Publication number: 20200381359Abstract: A semiconductor package includes a redistribution layer (RDL) structure, a first die, a molding compound and an interconnect structure. The first die is disposed on the RDL structure. The molding compound is disposed on the RDL structure. The interconnect structure electrically connects the first die to the RDL structure.Type: ApplicationFiled: June 3, 2019Publication date: December 3, 2020Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chun-Jun ZHUANG, Hsu-Nan FANG
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Patent number: 10797022Abstract: A semiconductor device package includes a first redistribution layer (RDL), a first die, a second die, a second RDL and an encapsulant. The first die is disposed on the first RDL and is electrically connected to the first RDL. The first die has a first electrical contact. The second die is disposed on the first RDL and is electrically connected to the first RDL. The second die has a first electrical contact. The second RDL is surrounded by the first RDL. The second RDL has a first electrical contact electrically connected to the first electrical contact of the first die and a second electrical contact electrically connected to the first electrical contact of the second die. A size of the first electrical contact of the second RDL is greater than a size of the second electrical contact of the second RDL.Type: GrantFiled: October 4, 2018Date of Patent: October 6, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Hsu-Nan Fang, Chun-Jun Zhuang, Yung I. Yeh, Ming-Chiang Lee
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Patent number: 10797019Abstract: A semiconductor package structure includes at least one semiconductor die, at least one conductive pillar, an encapsulant and a circuit structure. The semiconductor die has an active surface. The conductive pillar is disposed adjacent to the active surface of the semiconductor die. The encapsulant covers the semiconductor die and the conductive pillar. The encapsulant defines at least one groove adjacent to and surrounding the conductive pillar. The circuit structure is electrically connected to the conductive pillar.Type: GrantFiled: August 22, 2017Date of Patent: October 6, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Hsu-Nan Fang, Chun-Jun Zhuang
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Publication number: 20200194383Abstract: A semiconductor package includes a semiconductor die, a plurality of conductive bumps, a shielding layer, an encapsulant and a redistribution layer. The semiconductor die has an active surface, a backside surface and a lateral surface. The conductive bumps are disposed on the active surface of the semiconductor die. The shielding layer is disposed on the lateral surface of the semiconductor die. The encapsulant covers the shielding layer, and has a first surface and a second surface opposite to the first surface. The redistribution layer is disposed on the first surface of the encapsulant and electrically connected to the semiconductor die through the conductive bumps. The shielding layer is electrically connected to the redistribution layer.Type: ApplicationFiled: February 26, 2020Publication date: June 18, 2020Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Hsu-Nan FANG, Chun-Jun ZHUANG, Yung I. YEH
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Patent number: 10593630Abstract: A semiconductor package includes a semiconductor die, a plurality of conductive bumps, a shielding layer, an encapsulant and a redistribution layer. The semiconductor die has an active surface, a backside surface and a lateral surface. The conductive bumps are disposed on the active surface of the semiconductor die. The shielding layer is disposed on the lateral surface of the semiconductor die. The encapsulant covers the shielding layer, and has a first surface and a second surface opposite to the first surface. The redistribution layer is disposed on the first surface of the encapsulant and electrically connected to the semiconductor die through the conductive bumps. The shielding layer is electrically connected to the redistribution layer.Type: GrantFiled: May 11, 2018Date of Patent: March 17, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Hsu-Nan Fang, Chun-Jun Zhuang, Yung I. Yeh
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Publication number: 20190348371Abstract: A semiconductor package includes a semiconductor die, a plurality of conductive bumps, a shielding layer, an encapsulant and a redistribution layer. The semiconductor die has an active surface, a backside surface and a lateral surface. The conductive bumps are disposed on the active surface of the semiconductor die. The shielding layer is disposed on the lateral surface of the semiconductor die. The encapsulant covers the shielding layer, and has a first surface and a second surface opposite to the first surface. The redistribution layer is disposed on the first surface of the encapsulant and electrically connected to the semiconductor die through the conductive bumps. The shielding layer is electrically connected to the redistribution layer.Type: ApplicationFiled: May 11, 2018Publication date: November 14, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Hsu-Nan FANG, Chun-Jun ZHUANG, Yung I. YEH
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Patent number: 10475775Abstract: A semiconductor package device comprises a circuit layer, an electronic component disposed on the circuit layer, a package element and a first encapsulant. The package element is disposed on the circuit layer. The package element includes at least two electrical contacts electrically connected to the circuit layer. The first encapsulant is disposed on the circuit layer. The first encapsulant encapsulates the electronic component and the package element and exposes the electrical contacts of the package element.Type: GrantFiled: August 17, 2017Date of Patent: November 12, 2019Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Hsu-Nan Fang, Chun-Jun Zhuang