Patents by Inventor Chun-Jun ZHUANG

Chun-Jun ZHUANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12142576
    Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first passivation layer, a first metal layer and a first semiconductor die. The first metal layer is embedded in the first passivation layer. The first metal layer defines a first through-hole. The first semiconductor die is disposed on the first passivation layer.
    Type: Grant
    Filed: March 14, 2023
    Date of Patent: November 12, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsu-Nan Fang, Chun-Jun Zhuang
  • Publication number: 20230223352
    Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first passivation layer, a first metal layer and a first semiconductor die. The first metal layer is embedded in the first passivation layer. The first metal layer defines a first through-hole. The first semiconductor die is disposed on the first passivation layer.
    Type: Application
    Filed: March 14, 2023
    Publication date: July 13, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsu-Nan FANG, Chun-Jun ZHUANG
  • Patent number: 11605597
    Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first passivation layer, a first metal layer and a first semiconductor die. The first metal layer is embedded in the first passivation layer. The first metal layer defines a first through-hole. The first semiconductor die is disposed on the first passivation layer.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: March 14, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsu-Nan Fang, Chun-Jun Zhuang
  • Publication number: 20220367369
    Abstract: A semiconductor package structure includes at least one first semiconductor die, at least one second semiconductor die and an encapsulant. The first semiconductor die has a first surface and includes a plurality of first pillar structures disposed adjacent to the first surface. The second semiconductor die is electrically connected to the first semiconductor die. The encapsulant covers the first semiconductor die and the second semiconductor die. A lower surface of the encapsulant is substantially coplanar with an end surface of each of the first pillar structures and a surface of the second semiconductor die.
    Type: Application
    Filed: August 2, 2022
    Publication date: November 17, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsu-Nan FANG, Chun-Jun ZHUANG
  • Patent number: 11404380
    Abstract: A semiconductor package structure includes at least one first semiconductor die, at least one second semiconductor die and an encapsulant. The first semiconductor die has a first surface and includes a plurality of first pillar structures disposed adjacent to the first surface. The second semiconductor die is electrically connected to the first semiconductor die. The encapsulant covers the first semiconductor die and the second semiconductor die. A lower surface of the encapsulant is substantially coplanar with an end surface of each of the first pillar structures and a surface of the second semiconductor die.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: August 2, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsu-Nan Fang, Chun-Jun Zhuang
  • Patent number: 11257788
    Abstract: A semiconductor device package includes a first electronic component, a plurality of first conductive traces, a second electronic component, a plurality of second conductive traces and a plurality of first conductive structures. The first electronic component has a first active surface. The first conductive traces are disposed on and electrically connected to the first active surface. The second electronic component is stacked on the first electronic component. The second electronic component has an inactive surface facing the first active surface, a second active surface opposite the inactive surface, and at least one lateral surface connecting the second active surface and the inactive surface. The second conductive traces are electrically connected to the second active surface, and extending from the second active surface to the lateral surface. The first conductive structures are electrically connecting the second conductive traces to the first conductive traces, respectively.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: February 22, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsu-Nan Fang, Chun-Jun Zhuang
  • Patent number: 11211319
    Abstract: A device structure includes a first electronic structure and a plurality of first electric contacts. The first electronic structure has a surface and a center. The first electric contacts are exposed from the surface. The first electric contacts are spaced by a pitch that increases with increasing distance from the center.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: December 28, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsu-Nan Fang, Chun-Jun Zhuang, Chen Yuan Weng
  • Publication number: 20210327819
    Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first passivation layer, a first metal layer and a first semiconductor die. The first metal layer is embedded in the first passivation layer. The first metal layer defines a first through-hole. The first semiconductor die is disposed on the first passivation layer.
    Type: Application
    Filed: April 17, 2020
    Publication date: October 21, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsu-Nan FANG, Chun-Jun ZHUANG
  • Patent number: 11139252
    Abstract: A semiconductor package includes a semiconductor die, a plurality of conductive bumps, a shielding layer, an encapsulant and a redistribution layer. The semiconductor die has an active surface, a backside surface and a lateral surface. The conductive bumps are disposed on the active surface of the semiconductor die. The shielding layer is disposed on the lateral surface of the semiconductor die. The encapsulant covers the shielding layer, and has a first surface and a second surface opposite to the first surface. The redistribution layer is disposed on the first surface of the encapsulant and electrically connected to the semiconductor die through the conductive bumps. The shielding layer is electrically connected to the redistribution layer.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: October 5, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsu-Nan Fang, Chun-Jun Zhuang, Yung I. Yeh
  • Publication number: 20210193578
    Abstract: A semiconductor package structure includes at least one first semiconductor die, at least one second semiconductor die and an encapsulant. The first semiconductor die has a first surface and includes a plurality of first pillar structures disposed adjacent to the first surface. The second semiconductor die is electrically connected to the first semiconductor die. The encapsulant covers the first semiconductor die and the second semiconductor die. A lower surface of the encapsulant is substantially coplanar with an end surface of each of the first pillar structures and a surface of the second semiconductor die.
    Type: Application
    Filed: December 19, 2019
    Publication date: June 24, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsu-Nan FANG, Chun-Jun ZHUANG
  • Publication number: 20210159156
    Abstract: A device structure includes a first electronic structure and a plurality of first electric contacts. The first electronic structure has a surface and a center. The first electric contacts are exposed from the surface. The first electric contacts are spaced by a pitch that increases with increasing distance from the center.
    Type: Application
    Filed: November 21, 2019
    Publication date: May 27, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsu-Nan FANG, Chun-Jun ZHUANG, Chen Yuan WENG
  • Publication number: 20210091042
    Abstract: A semiconductor device package includes a first electronic component, a plurality of first conductive traces, a second electronic component, a plurality of second conductive traces and a plurality of first conductive structures. The first electronic component has a first active surface. The first conductive traces are disposed on and electrically connected to the first active surface. The second electronic component is stacked on the first electronic component. The second electronic component has an inactive surface facing the first active surface, a second active surface opposite the inactive surface, and at least one lateral surface connecting the second active surface and the inactive surface. The second conductive traces are electrically connected to the second active surface, and extending from the second active surface to the lateral surface. The first conductive structures are electrically connecting the second conductive traces to the first conductive traces, respectively.
    Type: Application
    Filed: September 24, 2019
    Publication date: March 25, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsu-Nan FANG, Chun-Jun ZHUANG
  • Patent number: 10886223
    Abstract: A semiconductor package includes a redistribution layer (RDL) structure, a first die, a molding compound and an interconnect structure. The first die is disposed on the RDL structure. The molding compound is disposed on the RDL structure. The interconnect structure electrically connects the first die to the RDL structure.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: January 5, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chun-Jun Zhuang, Hsu-Nan Fang
  • Publication number: 20200381359
    Abstract: A semiconductor package includes a redistribution layer (RDL) structure, a first die, a molding compound and an interconnect structure. The first die is disposed on the RDL structure. The molding compound is disposed on the RDL structure. The interconnect structure electrically connects the first die to the RDL structure.
    Type: Application
    Filed: June 3, 2019
    Publication date: December 3, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chun-Jun ZHUANG, Hsu-Nan FANG
  • Patent number: 10797022
    Abstract: A semiconductor device package includes a first redistribution layer (RDL), a first die, a second die, a second RDL and an encapsulant. The first die is disposed on the first RDL and is electrically connected to the first RDL. The first die has a first electrical contact. The second die is disposed on the first RDL and is electrically connected to the first RDL. The second die has a first electrical contact. The second RDL is surrounded by the first RDL. The second RDL has a first electrical contact electrically connected to the first electrical contact of the first die and a second electrical contact electrically connected to the first electrical contact of the second die. A size of the first electrical contact of the second RDL is greater than a size of the second electrical contact of the second RDL.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: October 6, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsu-Nan Fang, Chun-Jun Zhuang, Yung I. Yeh, Ming-Chiang Lee
  • Patent number: 10797019
    Abstract: A semiconductor package structure includes at least one semiconductor die, at least one conductive pillar, an encapsulant and a circuit structure. The semiconductor die has an active surface. The conductive pillar is disposed adjacent to the active surface of the semiconductor die. The encapsulant covers the semiconductor die and the conductive pillar. The encapsulant defines at least one groove adjacent to and surrounding the conductive pillar. The circuit structure is electrically connected to the conductive pillar.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: October 6, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsu-Nan Fang, Chun-Jun Zhuang
  • Publication number: 20200194383
    Abstract: A semiconductor package includes a semiconductor die, a plurality of conductive bumps, a shielding layer, an encapsulant and a redistribution layer. The semiconductor die has an active surface, a backside surface and a lateral surface. The conductive bumps are disposed on the active surface of the semiconductor die. The shielding layer is disposed on the lateral surface of the semiconductor die. The encapsulant covers the shielding layer, and has a first surface and a second surface opposite to the first surface. The redistribution layer is disposed on the first surface of the encapsulant and electrically connected to the semiconductor die through the conductive bumps. The shielding layer is electrically connected to the redistribution layer.
    Type: Application
    Filed: February 26, 2020
    Publication date: June 18, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsu-Nan FANG, Chun-Jun ZHUANG, Yung I. YEH
  • Patent number: 10593630
    Abstract: A semiconductor package includes a semiconductor die, a plurality of conductive bumps, a shielding layer, an encapsulant and a redistribution layer. The semiconductor die has an active surface, a backside surface and a lateral surface. The conductive bumps are disposed on the active surface of the semiconductor die. The shielding layer is disposed on the lateral surface of the semiconductor die. The encapsulant covers the shielding layer, and has a first surface and a second surface opposite to the first surface. The redistribution layer is disposed on the first surface of the encapsulant and electrically connected to the semiconductor die through the conductive bumps. The shielding layer is electrically connected to the redistribution layer.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: March 17, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsu-Nan Fang, Chun-Jun Zhuang, Yung I. Yeh
  • Publication number: 20190348371
    Abstract: A semiconductor package includes a semiconductor die, a plurality of conductive bumps, a shielding layer, an encapsulant and a redistribution layer. The semiconductor die has an active surface, a backside surface and a lateral surface. The conductive bumps are disposed on the active surface of the semiconductor die. The shielding layer is disposed on the lateral surface of the semiconductor die. The encapsulant covers the shielding layer, and has a first surface and a second surface opposite to the first surface. The redistribution layer is disposed on the first surface of the encapsulant and electrically connected to the semiconductor die through the conductive bumps. The shielding layer is electrically connected to the redistribution layer.
    Type: Application
    Filed: May 11, 2018
    Publication date: November 14, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsu-Nan FANG, Chun-Jun ZHUANG, Yung I. YEH
  • Patent number: 10475775
    Abstract: A semiconductor package device comprises a circuit layer, an electronic component disposed on the circuit layer, a package element and a first encapsulant. The package element is disposed on the circuit layer. The package element includes at least two electrical contacts electrically connected to the circuit layer. The first encapsulant is disposed on the circuit layer. The first encapsulant encapsulates the electronic component and the package element and exposes the electrical contacts of the package element.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: November 12, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsu-Nan Fang, Chun-Jun Zhuang