Patents by Inventor Chun Jung

Chun Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250149326
    Abstract: A method and system for effectively removing particles from semiconductor surfaces using a multi-beam laser-based approach. The invention employs a plurality of laser beams generated by a spatial light modulator, which create multiple light spots on a particle at various locations across its surface. By adjusting the phase of these laser beams, alternating clockwise and counterclockwise torsional forces are induced, generating rotational movement that weakens the adhesion between the particles and the semiconductor surface. The system utilizes a liquid crystal spatial light modulator to precisely control beam parameters, enhancing the ability to reduce adhesion forces due to van der Waals interactions or electrostatic forces. An automated optical inspection system provides real-time monitoring and feedback, ensuring precise manipulation and complete removal of particles.
    Type: Application
    Filed: January 13, 2025
    Publication date: May 8, 2025
    Inventors: Chun-Jung Chiu, Chun-Hsiung Chen, Wan-Chen Chuang
  • Publication number: 20250149380
    Abstract: A method includes adding a first additive to an electroplating solution, wherein the first additive is a relatively weak suppressing agent; adding a second additive to the electroplating solution, wherein the second additive is a relatively strong suppressing agent; adding a third additive to the electroplating solution, wherein the third additive is a leveling agent; and depositing copper using the electroplating solution, wherein most of the copper is nanotwinned grains having a (111)-orientation.
    Type: Application
    Filed: January 18, 2024
    Publication date: May 8, 2025
    Inventors: Ming-Da Cheng, Eugene Chow Chi Hao, Chang-Jung Hsueh, Chun-Fu Wu, Wen-Hsiung Lu
  • Publication number: 20250145040
    Abstract: A method for monitoring an electric vehicle charging apparatus is provided. A charging pile that includes a power meter and a processor is used to provide a charging current to an electric vehicle through a charging connector. The power meter detects the charging current to generate an initial current value and an initial power value that correspond to an initial charging time, and a present current value and a present power value that correspond to a present time, so that the processor calculates an initial resistance value and a present resistance value of the charging connector accordingly, and then calculates an estimated present temperature value of the charging connector based on the initial resistance value and the present resistance value. The estimated present temperature value is compared with an over-temperature threshold to determine whether to reduce the charging current.
    Type: Application
    Filed: November 2, 2023
    Publication date: May 8, 2025
    Inventors: Hsien-Ju WU, Chun-Chieh CHIU, Tai-Chang CHEN, Jinn-Feng JIANG, Chia-Lung HUANG, Mei-Jung CHEN
  • Publication number: 20250136118
    Abstract: A hybrid electric vehicle and a vibration control method thereof is provided. The vibration control method of the hybrid electric vehicle includes: receiving rotor angle information of a motor generated based on information detected by a resolver; receiving first engine rotation-angle information of an engine generated based on information detected by a cam angle sensor or a crank angle sensor; generating engine rotation-angle candidates based on the rotor angle information; and identifying a second engine rotation-angle based on the engine rotation-angle candidates and the first engine rotation-angle information.
    Type: Application
    Filed: March 20, 2024
    Publication date: May 1, 2025
    Applicants: HYUNDAI MOTOR COMPANY, KIA CORPORATION
    Inventors: Key Chun Park, Sung Il Jung
  • Publication number: 20250142376
    Abstract: A wireless system including a wireless station and an automatic frequency adjustment system and a method for controlling the same are disclosed. According to one embodiment of the present disclosure, the wireless system may include a wireless station including a beacon demodulator and an automatic frequency adjustment system having a database including identification information of a plurality of wireless local area network (LAN) access points (Aps), and the wireless station may be configured to: obtain information related to a first beacon frame by demodulating the first beacon frame transmitted from a first wireless LAN AP through the beacon demodulator and transmit the information related to the first beacon frame to the automatic frequency adjustment system.
    Type: Application
    Filed: October 25, 2024
    Publication date: May 1, 2025
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Seung Keun PARK, Sung Jun LEE, Bong Soo KIM, Jae Ho JUNG, Byung Su KANG, Hye Yeon KWON, Igor KIM, Kwang Chun LEE
  • Patent number: 12288716
    Abstract: A method includes forming a first metallic feature, forming a dielectric layer over the first metallic feature, etching the dielectric layer to form an opening, with a top surface of the first metallic feature being exposed through the opening, and performing a first treatment on the top surface of the first metallic feature. The first treatment is performed through the opening, and the first treatment is performed using a first process gas. After the first treatment, a second treatment is performed through the opening, and the second treatment is performed using a second process gas different from the first process gas. A second metallic feature is deposited in the opening.
    Type: Grant
    Filed: April 29, 2024
    Date of Patent: April 29, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hsien Huang, I-Li Chen, Pin-Wen Chen, Yuan-Chen Hsu, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
  • Publication number: 20250132223
    Abstract: Provided are devices and methods for forming devices. A device includes a workpiece; a thermal interface material (TIM) disposed over the workpiece; and a lid disposed over the workpiece, wherein the lid has an underside formed with a trench, and wherein a vertically extending portion of the TIM extends into the trench and a base portion of the TIM is located outside of the trench.
    Type: Application
    Filed: October 20, 2023
    Publication date: April 24, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Shiou Tsai, Chang-Jung Hsueh, Chun-Lung Jao, Po-Yao Lin, Kathy Wei Yan
  • Publication number: 20250118743
    Abstract: The present invention relates to a lithium secondary battery which includes a positive electrode including an overlithiated manganese-based oxide, in which an amount of manganese among total metals excluding lithium is greater than 50 mol % and a ratio (Li/Me) of the number of moles of the lithium to the number of moles of the total metals excluding the lithium is greater than 1, as a positive electrode active material; a negative electrode including a silicon-based negative electrode active material; a separator disposed between the positive electrode and the negative electrode; and an electrolyte, and satisfies Equation (1). 0.25 A ? B ? 0 . 6 ? A Equation ? ( 1 ) In Equation (1), A is a discharge curve area in a voltage range of 2.0 V to 4.6 V of a dQ/dV graph obtained by differentiating a graph of battery discharge capacity Q and voltage V after one cycle which are measured while charging the lithium secondary battery at 0.1 C to 4.
    Type: Application
    Filed: October 5, 2022
    Publication date: April 10, 2025
    Applicant: LG Energy Solution, Ltd.
    Inventors: Byung Chun Park, Wang Mo Jung, Sin Young Park, Hyuck Hur, Dong Hwi Kim
  • Publication number: 20250115425
    Abstract: A stocking vehicle is provided. The stocking vehicle is configured to perform a stocking operation to transfer a first product unit from a first location to a second location. The stocking vehicle includes a stocking component. The stocking vehicle includes a motor coupled to the stocking component to facilitate performance of the stocking operation by the stocking component. The stocking vehicle includes an energy storage device configured to supply first energy to the motor during a first state of the motor and store second energy of the motor during a second state of the motor.
    Type: Application
    Filed: October 9, 2023
    Publication date: April 10, 2025
    Inventors: Chun Cheng LIU, Guancyun Li, Ching-Jung Chang, Yi-Ching Lo
  • Publication number: 20250120158
    Abstract: Bipolar junction transistor (BJT) structures are provided. A BJT structure includes a semiconductor substrate, a collector region formed in the semiconductor substrate, a plurality of base regions formed over the collector region, a plurality of emitter regions formed over the collector region, a ring-shaped shallow trench isolation (STI) region formed in the collector region, a plurality of base conductive layers formed over the collector region and on opposite sides of the base regions, a plurality of sidewall dielectric layers formed on top surfaces of the base conductive layers and disposed vertically between the base conductive layers and upper portions of the emitter regions, and a plurality of base contacts formed on the base conductive layers. The base contacts are divided into a first group of base contacts disposed between the base regions and a second group of base contacts disposed between the base regions and the STI region.
    Type: Application
    Filed: December 16, 2024
    Publication date: April 10, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuan-Jung CHEN, Chun-Ming LIN, Tsung-Lin LEE, Shiuan-Jeng LIN, Hung-Lin CHEN
  • Patent number: 12272580
    Abstract: In an embodiment, a system, includes: a first pressurized load port interfaced with a workstation body; a second pressurized load port interfaced with the workstation body; the workstation body maintained at a set pressure level, wherein the workstation body comprises an internal material handling system configured to move a semiconductor workpiece within the workstation body between the first and second pressurized load ports at the set pressure level; a first modular tool interfaced with the first pressurized load port, wherein the first modular tool is configured to process the semiconductor workpiece; and a second modular tool interfaced with the second pressurized load port, wherein the second modular tool is configured to inspect the semiconductor workpiece processed by the first modular tool.
    Type: Grant
    Filed: January 3, 2024
    Date of Patent: April 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Jung Huang, Yung-Lin Hsu, Kuang Huan Hsu, Jeff Chen, Steven Huang, Yueh-Lun Yang
  • Patent number: 12272693
    Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate having a high-voltage (HV) region and a low-voltage (LV) region; forming a base on the HV region and fin-shaped structures on the LV region; forming a first insulating around the fin-shaped structures; removing the base, the first insulating layer, and part of the fin-shaped structures to form a first trench in the HV region and a second trench in the LV region; forming a second insulating layer in the first trench and the second trench; and planarizing the second insulating layer to form a first shallow trench isolation (STI) on the HV region and a second STI on the LV region.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: April 8, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Ya Chiu, Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Lin, Chien-Ting Lin, Chia-Jung Hsu, Chin-Hung Chen
  • Patent number: 12272600
    Abstract: A method includes forming a dielectric layer over an epitaxial source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the epitaxial source/drain region. A barrier layer is formed on a sidewall and a bottom of the opening. An oxidation process is performing on the sidewall and the bottom of the opening. The oxidation process transforms a portion of the barrier layer into an oxidized barrier layer and transforms a portion of the dielectric layer adjacent to the oxidized barrier layer into a liner layer. The oxidized barrier layer is removed. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with the liner layer.
    Type: Grant
    Filed: May 13, 2022
    Date of Patent: April 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pin-Wen Chen, Chang-Ting Chung, Yi-Hsiang Chao, Yu-Ting Wen, Kai-Chieh Yang, Yu-Chen Ko, Peng-Hao Hsu, Ya-Yi Cheng, Min-Hsiu Hung, Chun-Hsien Huang, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
  • Publication number: 20250113574
    Abstract: A method of forming a semiconductor structure, includes forming a fin structure over a substrate in a Z-direction; forming a dummy gate structure extending in a Y-direction and over the fin structure; and forming gate spacers on sidewalls of the dummy gate structure. The fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The method further includes removing a portion of the dummy gate structure to form a first trench that exposes upper portions of the gate spacers; forming an insulating material in the first trench; partially removing the insulating material to form insulating layers on sidewalls of the upper portions of the gate spacers; removing a remaining portion of the dummy gate structure to expose lower portions of the gate spacers; and partially etching the lower portions of the gate spacers.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Che CHEN, Yen-Cheng LAI, Pin-Jung CHEN, Ming-Heng TSAI, Feng-Ming CHANG, Chun-Jun LIN
  • Publication number: 20250113576
    Abstract: Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The structure includes a source/drain region disposed over a substrate, a gate electrode layer disposed over the substrate, a first gate spacer disposed between the gate electrode layer and the source/drain region, and a dielectric spacer disposed between the gate electrode layer and the source/drain region. A first portion of the dielectric spacer is in contact with a first portion of the first gate spacer. The structure further includes a sacrificial layer disposed between a second portion of the first gate spacer and a second portion of the dielectric spacer.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Inventors: Kuei-Yu KAO, Shih-Yao LIN, Chih-Chung CHIU, Chen-Chin LIAO, Chun-Yu LIN, Min-Chiao LIN, Yung-Chi CHANG, Li-Jung KUO
  • Patent number: 12266701
    Abstract: A high electron mobility transistor includes a substrate, a mesa structure disposed on the substrate, a passivation layer disposed on the mesa structure, and at least a contact structure disposed in the passivation layer and the mesa structure. The mesa structure includes a channel layer, a barrier layer on the channel layer, two opposite first edges extending along a first direction, and two opposite second edges extending along a second direction. The contact structure includes a body portion and a plurality of protruding portions. The body portion penetrates through the passivation layer. The protruding portions penetrate through the barrier layer and a portion of the channel layer. In a top view, the body portion overlaps the two opposite first edges of the mesa structure without overlapping the two opposite second edges of the mesa structure.
    Type: Grant
    Filed: May 18, 2023
    Date of Patent: April 1, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Tung Yeh, Chun-Liang Hou, Wen-Jung Liao, Chun-Ming Chang, Yi-Shan Hsu, Ruey-Chyr Lee
  • Patent number: 12261263
    Abstract: A lithium secondary battery includes a positive electrode, a negative electrode, a separator, and an electrolyte, wherein the positive electrode includes a positive electrode active material layer having a positive electrode active material containing an overlithiated manganese-based oxide represented by Formula 1 below, and the negative electrode includes a negative electrode active material layer having a silicon-based negative electrode active material, LiaNibCocMndMeO2??[Formula 1] wherein, M is at least one selected from the group consisting of Al, B, Co, W, Mg, V, Ti, Zn, Ga, In, Ru, Nb, Sn, Sr, and Zr, and 1<a, 0?b?0.5, 0?c?0.1, 0.5?d<1.0, and 0?e?0.2, and. Preferably, in the Formula 1, 1.1?a?1.5, 0.1?b?0.4, 0?c?0.05, 0.5?d?0.80, and 0?e?0.1.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: March 25, 2025
    Assignee: LG Energy Solution, Ltd.
    Inventors: Byung Chun Park, Yo Han Kwon, Je Young Kim, Seok Koo Kim, Wang Mo Jung, Yong Ju Lee, Chul Haeng Lee
  • Patent number: 12261086
    Abstract: A method for fabricating a semiconductor device includes first providing a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region, forming a HV device on the HV region, and forming a LV device on the LV region. Preferably, the HV device includes a first base on the substrate, a first gate dielectric layer on the first base, and a first gate electrode on the first gate dielectric layer. The LV device includes a fin-shaped structure on the substrate, and a second gate electrode on the fin-shaped structure, in which a top surface of the first gate dielectric layer is even with a top surface of the fin-shaped structure.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: March 25, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Lin, Chien-Ting Lin, Chun-Ya Chiu, Chia-Jung Hsu, Chin-Hung Chen
  • Publication number: 20250096150
    Abstract: The present application discloses an anti-electromagnetic interference wafer structure in the wafer processing stage; the anti-electromagnetic interference wafer structure comprises a digital processing unit area with a digital processing unit, an insulating layer, a conducting layer and a plurality of information connectivity points wherein the digital processing unit has a top surface on which the insulating layer and the information connectivity points are designed, the insulating layer has a top surface on which the conducting layer is coated, and the conducting layer is capable of absorbing electromagnetic interferences passed on to the conducting layer.
    Type: Application
    Filed: September 14, 2023
    Publication date: March 20, 2025
    Inventors: CHUN JUNG LIN, RUEI TING GU
  • Publication number: 20250096022
    Abstract: A semiconductor manufacturing system includes: a nozzle including a first channel that allows a fluid to flow through; a light source configured to emit light; and a light sensor configured to receive light, the light source and the light sensor being disposed within the first channel and opposite to each other. The semiconductor manufacturing system is configured to: emit light, by the light source, from within the nozzle toward a surface while the nozzle is dispensing the fluid; receive the light reflected from the surface by the light sensor, the emitted light and the reflected light adapted to be contained within the fluid; and examine a status of the reflected light. The emitted light and the reflected light propagate in a direction parallel to a longitudinal axis of the first channel.
    Type: Application
    Filed: December 5, 2024
    Publication date: March 20, 2025
    Inventors: KAI-LIN CHUANG, TSUNG-CHI CHEN, PEI-JUNG CHANG, CHUN-WEI HUANG, JUN XIU LIU