Patents by Inventor Chun-Kai Chen

Chun-Kai Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250099964
    Abstract: A nucleic acid detection device includes tube holders, an illumination module, a detection module and a driving module. The tube holders accommodates tubes, each containing a reagent and a magnetizable element. The illumination module includes light sources, a magnet and a casing, and the light sources and the magnet are installed on the casing. The driving module includes a motor, a lead screw and a slider. The lead screw is coupled to the motor and driven by the motor to rotate, and the slider is sleeved on the lead screw and has a reciprocating linear motion in response to a rotation of the lead screw. The illumination module is coupled to and moved together with the slider, so that the light sources and the magnet are synchronously driven by the motor and have reciprocating linear motions in a direction parallel to the lead screw.
    Type: Application
    Filed: November 8, 2023
    Publication date: March 27, 2025
    Inventors: Chun-Yen Kuo, Ying-Ting Chen, Yu-Jen Liu, Yu-Kai Kao, Yu-Hong Yen
  • Patent number: 12261086
    Abstract: A method for fabricating a semiconductor device includes first providing a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region, forming a HV device on the HV region, and forming a LV device on the LV region. Preferably, the HV device includes a first base on the substrate, a first gate dielectric layer on the first base, and a first gate electrode on the first gate dielectric layer. The LV device includes a fin-shaped structure on the substrate, and a second gate electrode on the fin-shaped structure, in which a top surface of the first gate dielectric layer is even with a top surface of the fin-shaped structure.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: March 25, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Lin, Chien-Ting Lin, Chun-Ya Chiu, Chia-Jung Hsu, Chin-Hung Chen
  • Publication number: 20250079172
    Abstract: A method includes forming a metal-containing hard mask layer over a dielectric layer, wherein the metal-containing hard mask layer has a Young's modulus greater than about 400 MPa and a tensile stress greater than about 600 MPa, patterning the metal-containing hard mask layer to form an opening in the metal-containing hard mask layer, and etching the dielectric layer using the metal-containing hard mask layer as an etching mask. The opening extends into the dielectric layer. The opening is filled with a conductive material to form a conductive feature. The metal-containing hard mask layer is then removed.
    Type: Application
    Filed: November 20, 2024
    Publication date: March 6, 2025
    Inventors: Chun-Kai Chen, JeiMing Chen, Tze-Liang Lee
  • Publication number: 20250081730
    Abstract: A display may include an array of pixels such as light-emitting diode pixels. The pixels may include multiple circuitry decks that each include one or more circuit components such as transistors, capacitors, and/or resistors. The circuitry decks may be vertically stacked. Each circuitry deck may include a planarization layer formed from a siloxane material that conforms to underlying components and provides a planar upper surface. In this way, circuitry components may be vertically stacked to mitigate the size of each pixel footprint. The circuitry components may include capacitors that include both a high-k dielectric layer and a low-k dielectric layer. The display pixel may include a via with a width of less than 1 micron.
    Type: Application
    Filed: June 26, 2024
    Publication date: March 6, 2025
    Inventors: Andrew Lin, Alper Ozgurluk, Chao Liang Chien, Cheuk Chi Lo, Chia-Yu Chen, Chien-Chung Wang, Chih Pang Chang, Chih-Hung Yu, Chih-Wei Chang, Chin Wei Hsu, ChinWei Hu, Chun-Kai Tzeng, Chun-Ming Tang, Chun-Yao Huang, Hung-Che Ting, Jung Yen Huang, Lungpao Hsin, Shih Chang Chang, Tien-Pei Chou, Wen Sheng Lo, Yu-Wen Liu, Yung Da Lai
  • Publication number: 20250058324
    Abstract: An automated molecular operating system includes at least one centrifuge tube carrying module, a transport module, a plurality of temperature control modules, a capping module, a magnetic field module and an automated processing module. The automated processing module is electrically connected to the transport module, the temperature control modules, the capping module and the magnetic field module, and controls the transport module to move the centrifuge tube carrying module, so that a centrifuge tube contained in the centrifuge tube carrying module makes a reaction in the temperature control modules, and the magnetic field module or the capping module is provided to the centrifuge tube according to requirements, such that a specimen in the centrifuge tube can be automatically subjected to nucleic acid extraction, nucleic acid amplification, primer labeling, reverse transcription or a combination thereof, thereby reducing manual operation errors and increasing the ease of operation.
    Type: Application
    Filed: November 17, 2023
    Publication date: February 20, 2025
    Inventors: Yi-Fang CHEN, Suz-Kai HSIUNG, Chun-Wei HUANG, Yin-Lin LI, Yu-Ying WU
  • Publication number: 20250062532
    Abstract: An antenna structure is disposed on a metal unit and includes a first slot, a second slot, a grounding portion and a short-circuiting portion. The first slot is formed on the metal unit along an axis direction and configured to receive a signal feed. The second slot is formed on the metal unit along the axis direction and separated from the first slot by a distance along the axis direction. The grounding portion is coupled to the metal unit. The short-circuiting portion crosses the second slot and is coupled to the grounding portion.
    Type: Application
    Filed: August 12, 2024
    Publication date: February 20, 2025
    Inventors: Chun-Kai CHEN, Cheng-Rui ZHANG, Jian-Zhong CHEN, Hong-Jun JIAN
  • Patent number: 12227619
    Abstract: The present invention provides a polyimide-based copolymer and electronic component and field effect transistor comprising the same. The polyimide-based copolymer comprises a copolymer of dianhydride and heterocyclic diamine, wherein the heterocyclic diamine has two benzene rings, and there are two ether bonds, two thioether bonds, or one ether bond and one thioether bond between the two benzene rings. The novel polyimide-based copolymer of the invention has excellent thermal-mechanical stability, has potential application prospects, and can be used as a substrate for flexible electronics.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: February 18, 2025
    Assignee: NATIONAL TAIWAN UNIVERSITY
    Inventors: Wen-Chang Chen, Mitsuru Ueda, Chun-Kai Chen, Yan-Cheng Lin
  • Patent number: 12228906
    Abstract: A calibration method for machine tools comprises: providing a workpiece on a machine tool; rotating the workpiece around a first rotation axis parallel to a main shaft of the machine tool and processing the workpiece by a first machining mode; measuring a first dimensional error of a shape of the workpiece along directions of first and second linear axes perpendicular to the first rotation axis; calculating a positional error of the first rotation axis according to the first dimensional error; rotating the workpiece around a second rotation axis perpendicular to the main shaft and processing the workpiece by a different second machining mode; measuring a second dimensional error of the shape of the workpiece along a direction of a third linear axis perpendicular to the second rotation axis; calculating a positional error of the second rotation axis according to the second dimensional error.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: February 18, 2025
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chung-Kai Wu, Chin-Ming Chen, Chun-Yu Tsai, Chi-Chen Lin, Chia-Chin Chuang, Ta-Jen Peng
  • Patent number: 12230595
    Abstract: A method of forming an integrated circuit structure includes forming a patterned passivation layer over a metal pad, with a top surface of the metal pad revealed through a first opening in the patterned passivation layer, and applying a polymer layer over the patterned passivation layer. The polymer layer is substantially free from N-Methyl-2-pyrrolidone (NMP), and comprises aliphatic amide as a solvent. The method further includes performing a light-exposure process on the polymer layer, performing a development process on the polymer layer to form a second opening in the polymer layer, wherein the top surface of the metal pad is revealed to the second opening, baking the polymer, and forming a conductive region having a via portion extending into the second opening.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: February 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Da Cheng, Yung-Ching Chao, Chun Kai Tzeng, Cheng Jen Lin, Chin Wei Kang, Yu-Feng Chen, Mirng-Ji Lii
  • Publication number: 20250042068
    Abstract: A method for processing a curved plastic panel is to first form a hard coating layer, an optical function layer, and a printing layer on a flat plastic substrate, and then cut it into a predetermined shape, and then use a hot pressing and curving device to perform a hot pressing and curving process to the flat plastic substrate in order to make it becoming a curved plastic substrate. The hot pressing and curving device can simultaneously perform hot pressing during the heating process, and has the functions of real-time monitoring of the local temperature and the local curvature forming state, and then feedback to the local heating and curvature forming mechanism for adjustments. The monitoring of temperature and curvature can be divided into multiple stages, which can be monitored stage by stage and adjusted for heating or curvature forming to improve production yield.
    Type: Application
    Filed: October 20, 2024
    Publication date: February 6, 2025
    Applicant: ENFLEX CORPORATION
    Inventors: Hsin Yuan CHEN, Chih Teng KU, Jui Lin HSU, Chun Kai WANG, Yu Ling CHIEN
  • Patent number: 12211747
    Abstract: A semiconductor device is disclosed. The device includes a source/drain feature formed over a substrate. A dielectric layer formed over the source/drain feature. A contact trench formed through the dielectric layer to expose the source/drain feature. A titanium nitride (TiN) layer deposited in the contact trench and a cobalt layer deposited over the TiN layer in the contact trench.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: January 28, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Hsien Huang, Hong-Mao Lee, Hsien-Lung Yang, Yu-Kai Chen, Wei-Jung Lin
  • Patent number: 12212926
    Abstract: A MEMS structure is provided. The MEMS structure includes a substrate and a backplate, the substrate has an opening portion, and the backplate is disposed on one side of the substrate and has acoustic holes. The MEMS structure also includes a diaphragm disposed between the substrate and the backplate, and the diaphragm extends across the opening portion of the substrate and includes outer ventilation holes and inner ventilation holes arranged in a concentric manner. The outer ventilation holes and the inner ventilation holes are relatively arranged in a ring shape and surround the center of the diaphragm. The MEMS structure further includes a pillar disposed between the backplate and the diaphragm. The pillar prevents the diaphragm from being electrically connected to the backplate.
    Type: Grant
    Filed: October 28, 2022
    Date of Patent: January 28, 2025
    Assignee: FORTEMEDIA, INC.
    Inventors: Wen-Shan Lin, Chun-Kai Mao, Chih-Yuan Chen, Jien-Ming Chen, Feng-Chia Hsu, Nai-Hao Kuo
  • Patent number: 12211751
    Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, an isolation structure on the SDB structure, a first spacer adjacent to the isolation structure, a metal gate adjacent to the isolation structure, a shallow trench isolation (STI around the fin-shaped structure, and a second isolation structure on the STI. Preferably, a top surface of the first spacer is lower than a top surface of the isolation structure and a bottom surface of the first spacer is lower than a bottom surface of the metal gate.
    Type: Grant
    Filed: December 28, 2023
    Date of Patent: January 28, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chi-Ting Wu, Chin-Hung Chen, Yu-Hsiang Lin
  • Publication number: 20250030218
    Abstract: The present application provides an optical device and a method of fabricating the same. The optical device include a semiconductor stack structure, an anti-reflective film and a highly-reflective film. The semiconductor stack structure is configured to generate a laser beam and emit the laser beam from its front facet while receiving an electric current. The anti-reflective film is disposed on the front facet of the semiconductor stack structure and configured to increase the transmittance (reduce a reflectivity) of the front facet to the laser beam. The highly-reflective film is disposed on a rear facet of the semiconductor stack structure and is configured to reduce a loss (increase a reflectivity) of the laser beam transmitted to the rear facet. The anti-reflective film and the highly-reflective film respectively have refractive indices greater than 2, and the highly-reflective film has a thickness greater than that of the anti-reflective film.
    Type: Application
    Filed: July 10, 2024
    Publication date: January 23, 2025
    Inventors: HORNG-SHYANG CHEN, THANT ZIN, HSUYING CHEN, CHUN-KO CHEN, CHIEN-KAI WANG, HAO-HSIANG TANG, NI YEH WU, SHIN-YI SHEN, RUEI-MING YANG
  • Patent number: 12207052
    Abstract: A MEMS structure is provided. The MEMS structure includes a substrate having an opening portion and a backplate disposed on one side of the substrate. The MEMS structure also includes a diaphragm disposed between the substrate and the backplate. The opening portion of the substrate is under the diaphragm, and an air gap is formed between the diaphragm and the backplate. The MEMS structure further includes a pillar structure connected with the backplate and the diaphragm and a protection post structure extending from the backplate into the air gap. From a top view of the backplate, the protection post structure surrounds the pillar structure.
    Type: Grant
    Filed: October 3, 2022
    Date of Patent: January 21, 2025
    Assignee: FORTEMEDIA, INC.
    Inventors: Chun-Kai Mao, Chih-Yuan Chen, Feng-Chia Hsu, Jien-Ming Chen, Wen-Shan Lin, Nai-Hao Kuo
  • Patent number: 12205824
    Abstract: In one exemplary aspect, the present disclosure is directed to a method for lithography patterning. The method includes providing a substrate and forming a target layer over the substrate. A patterning layer is formed by depositing a first layer having an organic composition; depositing a second layer including over 50 atomic percent of silicon; and depositing a photosensitive layer on the second layer. In some implementations, the second layer is deposited by ALD, CVD, or PVD processes.
    Type: Grant
    Filed: July 21, 2023
    Date of Patent: January 21, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Szu-Ping Tung, Chun-Kai Chen, Yi-Nien Su, Tze-Liang Lee
  • Patent number: 12183577
    Abstract: A method includes forming a metal-containing hard mask layer over a dielectric layer, wherein the metal-containing hard mask layer has a Young's modulus greater than about 400 MPa and a tensile stress greater than about 600 MPa, patterning the metal-containing hard mask layer to form an opening in the metal-containing hard mask layer, and etching the dielectric layer using the metal-containing hard mask layer as an etching mask. The opening extends into the dielectric layer. The opening is filled with a conductive material to form a conductive feature. The metal-containing hard mask layer is then removed.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: December 31, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Kai Chen, JeiMing Chen, Tze-Liang Lee
  • Publication number: 20240305162
    Abstract: A damper device and an electronic apparatus are provided. The damper device includes a first holder, a first damper component and a first gel. The first damper component includes a first protrusion part and a first bar part. The first protrusion part includes a first surface. The first bar part includes a first free end and a first fixed end. The first protrusion part is fixed on the first free end, the first fixed end is fixed on the first holder and the first surface protrudes outward from the first free end. The first free end and the first protrusion part are inserted into the first gel, and the first gel moves along the radial direction of the first bar part relative to the first bar part.
    Type: Application
    Filed: November 7, 2023
    Publication date: September 12, 2024
    Inventors: Chia-Ching HSU, Fu Yuan WU, Shang Yu HSU, Shao Chung CHANG, Meng Ting LIN, Chun Kai CHEN
  • Publication number: 20240071815
    Abstract: A method includes depositing a first dielectric layer over a first conductive feature, depositing a first mask layer over the first dielectric layer, and depositing a second mask layer over the first mask layer. A first opening is patterned in the first mask layer and the second mask layer, the first opening having a first width. A second opening is patterned in a bottom surface of the first opening, the second opening extending into the first dielectric layer, the second opening having a second width. The second width is less than the first width. The first opening is extended into the first dielectric layer and the second opening is extended through the first dielectric layer to expose a top surface of the first conductive feature.
    Type: Application
    Filed: October 31, 2023
    Publication date: February 29, 2024
    Inventors: Chun-Kai Chen, Jei Ming Chen, Tze-Liang Lee
  • Publication number: 20240021476
    Abstract: In an embodiment, a device includes: a source/drain region over a semiconductor substrate; a dielectric layer over the source/drain region, the dielectric layer including a first dielectric material; an inter-layer dielectric over the dielectric layer, the inter-layer dielectric including a second dielectric material and an impurity, the second dielectric material different from the first dielectric material, a first portion of the inter-layer dielectric having a first concentration of the impurity, a second portion of the inter-layer dielectric having a second concentration of the impurity, the first concentration less than the second concentration; and a source/drain contact extending through the inter-layer dielectric and the dielectric layer to contact the source/drain region, the first portion of the inter-layer dielectric disposed between the source/drain contact and the second portion of the inter-layer dielectric.
    Type: Application
    Filed: January 6, 2023
    Publication date: January 18, 2024
    Inventors: Yu-Lien Huang, Tze-Liang Lee, Jr-Hung Li, Chun-Kai Chen