Abstract: An electro-acoustical transducer device is disclosed, which includes: a hollow disk body that generally defines an axis of propagation, the hollow disk body comprising: a pair of plate members extending substantially perpendicular to the axis of propagation, each provided with a central transmitting port arranged about the axis of propagation, and a peripheral enclosure jointing the pair of plate members at the respective outer edge portions thereof, thereby defining a chamber of resonance between the pair of plate members; wherein a ring-opening about the axis of propagation that enables access to the chamber of resonance is formed between the central transmitting ports of the plate members.

Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, an isolation structure on the SDB structure, a first spacer adjacent to the isolation structure, a metal gate adjacent to the isolation structure, a shallow trench isolation (STI around the fin-shaped structure, and a second isolation structure on the STI. Preferably, a top surface of the first spacer is lower than a top surface of the isolation structure and a bottom surface of the first spacer is lower than a bottom surface of the metal gate.

Abstract: An acute kidney injury predicting system and a method thereof are proposed. A processor reads the data to be tested, the detection data, the machine learning algorithm and the risk probability comparison table from a main memory. The processor trains the detection data according to the machine learning algorithm to generate an acute kidney injury prediction model, and inputs the data to be tested into the acute kidney injury prediction model to generate an acute kidney injury characteristic risk probability and a data sequence table. The data sequence table lists the data to be tested in sequence according to a proportion of each of the data to be tested in the acute kidney injury characteristics. The processor selects one of the medical treatment data from the risk probability comparison table according to the acute kidney injury characteristic risk probability.

Abstract: In an embodiment, a device includes: a gate electrode; a epitaxial source/drain region adjacent the gate electrode; one or more inter-layer dielectric (ILD) layers over the epitaxial source/drain region; a first source/drain contact extending through the ILD layers, the first source/drain contact connected to the epitaxial source/drain region; a contact spacer surrounding the first source/drain contact; and a void disposed between the contact spacer and the ILD layers.

Abstract: A casing structure with functionality of effective thermal management is disclosed, which consists of a casing member, a low thermal conductivity medium, a second heat spreader, and a first heat spreader. When a user operates the electronic device, heat generated from CPU and/or GPU is transferred to the second heat spreader via the first heat spreader, and then is two-dimensionally spread in the second heat spreader. Consequently, the heat is dissipated away from the casing member to air due to the outstanding thermal radiation ability of the casing member. The low thermal conductivity medium is adopted for controlling a heat transfer of heat transferring paths from the heat source and ends to the casing member. By applying the casing structure in an electronic device by a form of a top casing and/or a back casing, an outer surface temperature of the casing member can be well controlled.

Abstract: A method includes depositing a first dielectric layer over a first conductive feature, depositing a first mask layer over the first dielectric layer, and depositing a second mask layer over the first mask layer. A first opening is patterned in the first mask layer and the second mask layer, the first opening having a first width. A second opening is patterned in a bottom surface of the first opening, the second opening extending into the first dielectric layer, the second opening having a second width. The second width is less than the first width. The first opening is extended into the first dielectric layer and the second opening is extended through the first dielectric layer to expose a top surface of the first conductive feature.

Abstract: A virtual reality tracker includes a first part and a second part. The first part includes a plurality of first light-emitting diodes (LEDs) and an inner measurement unit (IMU). The inertial measurement unit is used for measuring the acceleration and the triaxial angular velocity of the first part. The second part includes a plurality of second light-emitting diodes. Moreover, the first part and the second part are connected by a flexible component.

Abstract: In an embodiment, a device includes: a source/drain region over a semiconductor substrate; a dielectric layer over the source/drain region, the dielectric layer including a first dielectric material; an inter-layer dielectric over the dielectric layer, the inter-layer dielectric including a second dielectric material and an impurity, the second dielectric material different from the first dielectric material, a first portion of the inter-layer dielectric having a first concentration of the impurity, a second portion of the inter-layer dielectric having a second concentration of the impurity, the first concentration less than the second concentration; and a source/drain contact extending through the inter-layer dielectric and the dielectric layer to contact the source/drain region, the first portion of the inter-layer dielectric disposed between the source/drain contact and the second portion of the inter-layer dielectric.

Abstract: A method includes depositing a first dielectric layer over a first conductive feature, depositing a first mask layer over the first dielectric layer, and depositing a second mask layer over the first mask layer. A first opening is patterned in the first mask layer and the second mask layer, the first opening having a first width. A second opening is patterned in a bottom surface of the first opening, the second opening extending into the first dielectric layer, the second opening having a second width. The second width is less than the first width. The first opening is extended into the first dielectric layer and the second opening is extended through the first dielectric layer to expose a top surface of the first conductive feature.

Abstract: In one exemplary aspect, the present disclosure is directed to a method for lithography patterning. The method includes providing a substrate and forming a target layer over the substrate. A patterning layer is formed by depositing a first layer having an organic composition; depositing a second layer including over 50 atomic percent of silicon; and depositing a photosensitive layer on the second layer. In some implementations, the second layer is deposited by ALD, CVD, or PVD processes.

Abstract: In one exemplary aspect, the present disclosure is directed to a method for lithography patterning. The method includes providing a substrate and forming a target layer over the substrate. A patterning layer is formed by depositing a first layer having an organic composition; depositing a second layer including over 50 atomic percent of silicon; and depositing a photosensitive layer on the second layer. In some implementations, the second layer is deposited by ALD, CVD, or PVD processes.

Abstract: A method includes depositing a first dielectric layer over a first conductive feature, depositing a first mask layer over the first dielectric layer, and depositing a second mask layer over the first mask layer. A first opening is patterned in the first mask layer and the second mask layer, the first opening having a first width. A second opening is patterned in a bottom surface of the first opening, the second opening extending into the first dielectric layer, the second opening having a second width. The second width is less than the first width. The first opening is extended into the first dielectric layer and the second opening is extended through the first dielectric layer to expose a top surface of the first conductive feature.

Abstract: A method includes forming a metal-containing hard mask layer over a dielectric layer, wherein the metal-containing hard mask layer has a Young's modulus greater than about 400 MPa and a tensile stress greater than about 600 MPa, patterning the metal-containing hard mask layer to form an opening in the metal-containing hard mask layer, and etching the dielectric layer using the metal-containing hard mask layer as an etching mask. The opening extends into the dielectric layer. The opening is filled with a conductive material to form a conductive feature. The metal-containing hard mask layer is then removed.

Abstract: In one exemplary aspect, the present disclosure is directed to a method for lithography patterning. The method includes providing a substrate and forming a target layer over the substrate. A patterning layer is formed by depositing a first layer having an organic composition; depositing a second layer including over 50 atomic percent of silicon; and depositing a photosensitive layer on the second layer. In some implementations, the second layer is deposited by ALD, CVD, or PVD processes.

Abstract: In one exemplary aspect, the present disclosure is directed to a method for lithography patterning. The method includes providing a substrate and forming a target layer over the substrate. A patterning layer is formed by depositing a first layer having an organic composition having a composition including at least 50 atomic percentage carbon; depositing a second layer including silicon; and depositing a photosensitive layer on the second layer. In some implementations, the first layer is deposited by ALD, CVD, or PVD processes.

Abstract: The present invention provides a polyimide-based copolymer and electronic component and field effect transistor comprising the same. The polyimide-based copolymer comprises a copolymer of dianhydride and heterocyclic diamine, wherein the heterocyclic diamine has two benzene rings, and there are two ether bonds, two thioether bonds, or one ether bond and one thioether bond between the two benzene rings. The novel polyimide-based copolymer of the invention has excellent thermal-mechanical stability, has potential application prospects, and can be used as a substrate for flexible electronics.

Abstract: A method includes forming a carbon-containing layer with a carbon atomic percentage greater than about 25 percent over a first hard mask layer, forming a capping layer over the carbon-containing layer, forming a first photo resist over the capping layer, and etching the capping layer and the carbon-containing layer using the first photo resist as a first etching mask. The first photo resist is then removed. A second photo resist is formed over the capping layer. The capping layer and the carbon-containing layer are etched using the second photo resist as a second etching mask. The second photo resist is removed. A third photo resist under the carbon-containing layer is etched using the carbon-containing layer as etching mask. A dielectric layer underlying the third photo resist is etched to form via openings using the third photo resist as etching mask. The via openings are filled with a conductive material.

Abstract: A hard mask formed over a patterned photoresist layer in a tri-layer photoresist and a method for patterning a target layer using the same are disclosed. In an embodiment, a method includes depositing a photoresist layer over a first hard mask layer; patterning the photoresist layer to form a plurality of openings in the photoresist layer; depositing a second hard mask layer over the photoresist layer, the second hard mask layer filling the plurality of openings, the second hard mask layer having a first etch selectivity relative to the first hard mask layer, the photoresist layer having a second etch selectivity relative to the first hard mask layer, the first etch selectivity being greater than the second etch selectivity; planarizing the second hard mask layer; removing the photoresist layer; and etching the first hard mask layer using the second hard mask layer as a mask.

Abstract: A hard mask formed over a patterned photoresist layer in a tri-layer photoresist and a method for patterning a target layer using the same are disclosed. In an embodiment, a method includes depositing a photoresist layer over a first hard mask layer; patterning the photoresist layer to form a plurality of openings in the photoresist layer; depositing a second hard mask layer over the photoresist layer, the second hard mask layer filling the plurality of openings, the second hard mask layer having a first etch selectivity relative to the first hard mask layer, the photoresist layer having a second etch selectivity relative to the first hard mask layer, the first etch selectivity being greater than the second etch selectivity; planarizing the second hard mask layer; removing the photoresist layer; and etching the first hard mask layer using the second hard mask layer as a mask.

Abstract: A method includes forming a carbon-containing layer with a carbon atomic percentage greater than about 25 percent over a first hard mask layer, forming a capping layer over the carbon-containing layer, forming a first photo resist over the capping layer, and etching the capping layer and the carbon-containing layer using the first photo resist as a first etching mask. The first photo resist is then removed. A second photo resist is formed over the capping layer. The capping layer and the carbon-containing layer are etched using the second photo resist as a second etching mask. The second photo resist is removed. A third photo resist under the carbon-containing layer is etched using the carbon-containing layer as etching mask. A dielectric layer underlying the third photo resist is etched to form via openings using the third photo resist as etching mask. The via openings are filled with a conductive material.