Abstract: Disclosed are a light-emitting device and a display device including the same. An emissive layer is formed so as to have a dual-layer structure, the triplet energy level of a dopant of a first emissive layer adjacent to a hole transport layer is greater than the triplet energy level of a first host in the first emissive layer, and the triplet energy level of the first host is greater than the triplet energy level of a second host of a second emissive layer, whereby triplet excitons generated in the first emissive layer are recycled to the second emissive layer so as to be reused for light emission.

Abstract: A thin film deposition apparatus mounted with a Raman analysis system is discussed. The thin film deposition apparatus includes a reaction chamber providing an inner space for forming a thin film. An opening is formed on the thin film deposition apparatus to be connected to the reaction chamber, and the opening is closed by a window through which light can be transmitted.

Abstract: A method of manufacturing a perovskite multilayered structure includes providing a substrate, forming a first perovskite layer on the substrate, forming a second perovskite layer by a reaction between the halogen compounds and at least one of the metal halides, the metal oxides, or the metal sulfides.

Abstract: A method for surface planarization of an object using a light source of a specific wavelength according to an embodiment includes: providing an object in a main chamber; injecting an etching gas into the main chamber; inputting the light source of a specific wavelength onto a surface of the object; and controlling a temperature of the object. According to the method, it is possible to minimize the side effects such as scratches or contamination of the sample that occur in a conventional chemical-mechanical planarization process. In addition, it is possible to allow precise planarization in nanometers (nm) and simultaneously perform planarization to a side surface of a device as well as a large-sized surface, thereby reducing cost and time required for the planarization process. Moreover, since the surface roughness and the electrical conductivity are improved, it is possible to increase the efficiency and output of the LED device.

Abstract: A method of manufacturing a perovskite multilayered structure includes providing a substrate, forming a first perovskite layer on the substrate, forming a second perovskite layer by a reaction between the halogen compounds and at least one of the metal halides, the metal oxides, or the metal sulfides.

Abstract: The present invention provides a chalcogenide phase-change material represented by the following Chemical Formula 1, and a memory device including the same. Ma(AxSbyTe(1-x-y))b??[Chemical Formula 1] In Chemical Formula 1, M denotes an element having a doping formation energy ?Ef in a range of ?3 eV/atom to 0.5 eV/atom, A denotes indium (In) or germanium (Ge), a and b are each positive numbers and selected to satisfy a+b=1, x ranges from 0.15 to 0.3, and y ranges from 0.05 to 0.25.

Abstract: The present invention provides a chalcogenide phase-change material represented by the following Chemical Formula 1, and a memory device including the same. Ma(AxSbyTe(1-x-y))b??[Chemical Formula 1] In Chemical Formula 1, M denotes an element having a doping formation energy ?Ef in a range of ?3 eV/atom to 0.5 eV/atom, A denotes indium (In) or germanium (Ge), a and b are each positive numbers and selected to satisfy a+b=1, x ranges from 0.15 to 0.3, and y ranges from 0.05 to 0.25.

Abstract: A method for surface planarization of an object using a light source of a specific wavelength according to an embodiment includes: providing an object in a main chamber; injecting an etching gas into the main chamber; inputting the light source of a specific wavelength onto a surface of the object; and controlling a temperature of the object. According to the method, it is possible to minimize the side effects such as scratches or contamination of the sample that occur in a conventional chemical-mechanical planarization process. In addition, it is possible to allow precise planarization in nanometers (nm) and simultaneously perform planarization to a side surface of a device as well as a large-sized surface, thereby reducing cost and time required for the planarization process. Moreover, since the surface roughness and the electrical conductivity are improved, it is possible to increase the efficiency and output of the LED device.

Abstract: A method for preparing a ZnO nanocrystal directly on a silicon substrate includes the steps of: (S1) forming a Zn—Si—O composite thin film on the silicon substrate; and (S2) thermally treating the obtained thin film. Particularly, ZnO nanocrystals are formed in an amorphous Zn—Si—O composite thin film by controlling the composition of the Zn—Si—O composite thin film and heating temperature thereof. With the present invention method for preparing a ZnO nanocrystal directly on a silicon substrate, more possibilities are opened up for the applications of ZnO nanocrystals to an optoelectronic device in use of a silicon substrate.

Abstract: A method for preparing a ZnO nanocrystal directly on a silicon substrate includes the steps of: (S1) forming a Zn—Si—O composite thin film on the silicon substrate; and (S2) thermally treating the obtained thin film. Particularly, ZnO nanocrystals are formed in an amorphous Zn—Si—O composite thin film by controlling the composition of the Zn—Si—O composite thin film and heating temperature thereof. With the present invention method for preparing a ZnO nanocrystal directly on a silicon substrate, more possibilities are opened up for the applications of ZnO nanocrystals to an optoelectronic device in use of a silicon substrate.

Abstract: Provided is a phase-change RAM containing a substrate, a lower electrode, a phase-change material, an upper electrode and a thermal dissipation layer, wherein the thermal dissipation layer contains an aluminum-nitride thermal dissipation layer having a high heat conductivity, and the lower electrode contains a titanium-nitride electrode which generates a great amount of heat generated using a small amount of current and has a low heat conductivity, whereby heat generated between the phase-change material and the electrode is not transferred to the interior of a device but fast dissipated to the exterior thereof, so as to enable a high speed operation using low current and improve reliability of the device.

Abstract: A fabrication method of a self-aligned ferroelectric gate transistor using a buffer layer of high etching selectivity is disclosed. A stacked structure is formed with a buffer layer with high etching selectivity inserted between a silicon substrate and a ferroelectric layer, and etching is performed on a portion where a source and a drain will be formed and then stopped at the buffer layer, thereby fabricating a self-aligned ferroelectric gate transistor without damage to the silicon thin film, and thus, an integration degree of a chip can be improved.

Abstract: Provided is a phase-change RAM containing a substrate, a lower electrode, a phase-change material, an upper electrode and a thermal dissipation layer, wherein the thermal dissipation layer contains an aluminum-nitride thermal dissipation layer having a high heat conductivity, and the lower electrode contains a titanium-nitride electrode which generates a great amount of heat generated using a small amount of current and has a low heat conductivity, whereby heat generated between the phase-change material and the electrode is not transferred to the interior of a device but fast dissipated to the exterior thereof, so as to enable a high speed operation using low current and improve reliability of the device.

Abstract: A fabrication method of a self-aligned ferroelectric gate transistor using a buffer layer of high etching selectivity is disclosed. A stacked structure is formed with a buffer layer with high etching selectivity inserted between a silicon substrate and a ferroelectric layer, and etching is performed on a portion where a source and a drain will be formed and then stopped at the buffer layer, thereby fabricating a self-aligned ferroelectric gate transistor without damage to the silicon thin film, and thus, an integration degree of a chip can be improved.

Abstract: The driving circuit for an NDRO-FRAM includes several NDRO-FRAM (Non Destructive Non Volatile Ferroelectric Random Access Memory) cells each having a drain, a bulk, a source and a gate and arranged as a matrix. A plurality of reading word lines are separately connected to each drain of the NDRO-FRAM cells arranged in columns, and a plurality of writing word lines are separately connected to each bulk of the NDRO-FRM cells arranged in columns. Several data level transmission circuits for transmitting a data level of the NDRO-FRAM cells are also included, which are connected to a plurality of data level transmission circuits. Accordingly, the present invention is capable of reading and writing of data on the NDRO-FRAM cells.

Abstract: The driving circuit for an NDRO-FRAM includes several NDRO-FRAM (Non Destructive Non Volatile Ferroelectric Random Access Memory) cells each having a drain, a bulk, a source and a gate and arranged as a matrix. A plurality of reading word lines are separately connected to each drain of the NDRO-FRAM cells arranged in columns, and a plurality of writing word lines are separately connected to each bulk of the NDRO-FRM cells arranged in columns. Several data level transmission circuits for transmitting a data level of the NDRO-FRAM cells are also included, which are connected to a plurality of data level transmission circuits. Accordingly, the present invention is capable of reading and writing of data on the NDRO-FRAM cells.