Abstract: A neural network based method places flexible blocks on a chip canvas in an integrated circuit (IC) design. The neural network receives an input describing geometric features of a flexible block to be placed on the chip canvas. The geometric features includes an area size and multiple aspect ratios. The neural network generates a probability distribution over locations on the chip canvas and the aspect ratios of the flexible block. Based on the probability distribution, a location on the chip canvas is selected for placing the flexible block with a chosen aspect ratio.

Abstract: A neural network is used to place macros on a chip canvas in an integrated circuit (IC) design. The macros are first clustered into multiple macro clusters. Then the neural network generates a probability distribution over locations on a grid and aspect ratios of a macro cluster. The grid represents the chip canvas and is formed by rows and columns of grid cells. The macro cluster is described by at least an area size, aspect ratios, and wire connections. Action masks are generated for respective ones of the aspect ratios to block out a subset of unoccupied grid cells based on design rules that optimize macro placement. Then, by applying the action masks on the probability distribution, a masked probability distribution is generated. Based on the masked probability distribution, a location on the grid is selected for placing the macro cluster with a chosen aspect ratio.