Patents by Inventor Chun-Kuang Chen
Chun-Kuang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12145087Abstract: A filter is used for removing metallic contaminants in a solvent used in microcircuit fabrication. The filter includes a filter housing including a filter membrane for filtering solvent including metallic contaminants, and a magnet arranged about the filter housing and configured to generate a magnetic field to attract the metallic contaminants prior to the metallic contaminants entering the filter membrane. The magnet is arranged such that the magnetic field of the magnet is greater in a periphery of the filter housing compared to a central portion of the filter housing.Type: GrantFiled: July 26, 2022Date of Patent: November 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsuan-Ying Mai, Hui-Chun Lee, Chun-Kuang Chen, Tung-Hung Feng
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Publication number: 20240375029Abstract: A filter is used for removing metallic contaminants in a solvent used in microcircuit fabrication. The filter includes a filter housing including a filter membrane for filtering solvent including metallic contaminants, and a magnet arranged about the filter housing and configured to generate a magnetic field to attract the metallic contaminants prior to the metallic contaminants entering the filter membrane. The magnet is arranged such that the magnetic field of the magnet is greater in a periphery of the filter housing compared to a central portion of the filter housing.Type: ApplicationFiled: July 24, 2024Publication date: November 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsuan-Ying MAI, Hui-Chun LEE, Chun-Kuang CHEN, Tung-Hung FENG
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Publication number: 20240371639Abstract: A test wafer is placed inside a baking module and is baked. Via one or more temperature sensors, a cumulative heat amount delivered to the test wafer during the baking is measured. The measured cumulative heat amount is compared with a predefined cumulative heat amount threshold. In response to the comparing indicating that the measured cumulative heat amount is within the predefined cumulative heat amount threshold, it is determined that the baking module is qualified for actual semiconductor fabrication. In response to the comparing indicating that the measured cumulative heat amount is outside of the predefined cumulative heat amount threshold, it is determined that the baking module is not qualified for actual semiconductor fabrication.Type: ApplicationFiled: July 12, 2024Publication date: November 7, 2024Inventors: Chia-Cheng Chao, Chung-Cheng Wang, Chun-Kuang Chen
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Patent number: 12078921Abstract: A phase-shift reticle for a photolithography process in semiconductor fabrication is provided. The reticle includes a substrate, a reflective structure, a pattern defining layer and a phase shifter. The reflective structure is disposed over the substrate. The pattern defining layer includes a first material and is deposited over the reflective structure. The pattern defining layer comprises a pattern trench. The phase shifter includes a second material and disposed in the pattern trench. A transmittance of the second material is different from a transmittance of the first material.Type: GrantFiled: November 18, 2021Date of Patent: September 3, 2024Assignee: ENTEGRIS, INC.Inventors: Tse-An Yeh, Jun-Fei Zheng, Montray Leavy, Chun Kuang Chen
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Patent number: 12062542Abstract: A test wafer is placed inside a baking module and is baked. Via one or more temperature sensors, a cumulative heat amount delivered to the test wafer during the baking is measured. The measured cumulative heat amount is compared with a predefined cumulative heat amount threshold. In response to the comparing indicating that the measured cumulative heat amount is within the predefined cumulative heat amount threshold, it is determined that the baking module is qualified for actual semiconductor fabrication. In response to the comparing indicating that the measured cumulative heat amount is outside of the predefined cumulative heat amount threshold, it is determined that the baking module is not qualified for actual semiconductor fabrication.Type: GrantFiled: January 10, 2022Date of Patent: August 13, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Cheng Chao, Chung-Cheng Wang, Chun-Kuang Chen
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Publication number: 20240178002Abstract: A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench.Type: ApplicationFiled: February 5, 2024Publication date: May 30, 2024Inventors: Yung-Sung Yen, Chung-Ju Lee, Chun-Kuang Chen, Chia-Tien Wu, Ta-Ching Yu, Kuei-Shun Chen, Ru-Gun Liu, Shau-Lin Shue, Tsai-Sheng Gau, Yung-Hsu Wu
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Publication number: 20240096867Abstract: A semiconductor structure is provided and includes a first gate structure, a second gate structure, and at least one local interconnect that extend continuously across a non-active region from a first active region to a second active region. The semiconductor structure further includes a first separation spacer disposed on the first gate structure and first vias on the first gate structure. The first vias are arranged on opposite sides of the first separation spacer are isolated from each other and apart from the first separation spacer by different distances.Type: ApplicationFiled: December 1, 2023Publication date: March 21, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Charles Chew-Yuen YOUNG, Chih-Liang CHEN, Chih-Ming LAI, Jiann-Tyng TZENG, Shun-Li CHEN, Kam-Tou SIO, Shih-Wei PENG, Chun-Kuang CHEN, Ru-Gun LIU
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Patent number: 11901188Abstract: Exemplary methods of patterning a device layer are described, including operations of patterning a protector layer and forming a first opening in a first patterning layer to expose a first portion of the protector layer and a first portion of the hard mask layer, which are then are exposed to a first etch to form a first opening in the first portion of the hard mask layer. A second opening is formed in a second patterning layer to expose a second portion of the protector layer and a second portion of the hard mask layer. The second portion of the protector layer and the second portion of the hard mask layer are exposed to an etch to form a second opening in the second portion of the hard mask layer. Exposed portions of the device layer are then etched through the first opening and the second opening.Type: GrantFiled: March 28, 2022Date of Patent: February 13, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chi-Cheng Hung, Chun-Kuang Chen, De-Fang Chen, Wei-Liang Lin, Yu-Tien Shen
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Patent number: 11894238Abstract: A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench.Type: GrantFiled: July 11, 2022Date of Patent: February 6, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yung-Sung Yen, Chung-Ju Lee, Chun-Kuang Chen, Chia-Tien Wu, Ta-Ching Yu, Kuei-Shun Chen, Ru-Gun Liu, Shau-Lin Shue, Tsai-Sheng Gau, Yung-Hsu Wu
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Patent number: 11862623Abstract: A method is provided, including the following operations: arranging a first gate structure extending continuously above a first active region and a second active region of a substrate; arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure, wherein the first gate via and the second gate via are arranged above the first active region and the second active region respectively; and arranging a first local interconnect between the first active region and the second active region, wherein the first local interconnect is electrically coupled to a first contact disposed on the first active region and a second contact disposed on the second active region.Type: GrantFiled: February 10, 2023Date of Patent: January 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Charles Chew-Yuen Young, Chih-Liang Chen, Chih-Ming Lai, Jiann-Tyng Tzeng, Shun-Li Chen, Kam-Tou Sio, Shih-Wei Peng, Chun-Kuang Chen, Ru-Gun Liu
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Publication number: 20230187434Abstract: A method is provided, including the following operations: arranging a first gate structure extending continuously above a first active region and a second active region of a substrate; arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure, wherein the first gate via and the second gate via are arranged above the first active region and the second active region respectively; and arranging a first local interconnect between the first active region and the second active region, wherein the first local interconnect is electrically coupled to a first contact disposed on the first active region and a second contact disposed on the second active region.Type: ApplicationFiled: February 10, 2023Publication date: June 15, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Charles Chew-Yuen YOUNG, Chih-Liang CHEN, Chih-Ming LAI, Jiann-Tyng TZENG, Shun-Li CHEN, Kam-Tou SIO, Shih-Wei PENG, Chun-Kuang CHEN, Ru-Gun LIU
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Patent number: 11666838Abstract: A filter is used for removing metallic contaminants in a solvent used in microcircuit fabrication. The filter includes a filter housing including a filter membrane for filtering solvent including metallic contaminants, and a magnet arranged about the filter housing and configured to generate a magnetic field to attract the metallic contaminants prior to the metallic contaminants entering the filter membrane. The magnet is arranged such that the magnetic field of the magnet is greater in a periphery of the filter housing compared to a central portion of the filter housing.Type: GrantFiled: August 22, 2019Date of Patent: June 6, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsuan-Ying Mai, Hui-Chun Lee, Chun-Kuang Chen, Tung-Hung Feng
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Patent number: 11594528Abstract: A layout modification method for fabricating a semiconductor device is provided. The layout modification method includes calculating uniformity of critical dimensions of first and second portions in a patterned layer by using a layout for an exposure manufacturing process to produce the semiconductor device. A width of the first and second portions equals a penumbra size of the exposure manufacturing process. The penumbra size is utilized to indicate which area of the patterned layer is affected by light leakage exposure from another exposure manufacturing process. The layout modification method further includes compensating non-uniformity of the first and second portions of the patterned layer according to the uniformity of critical dimensions to generate a modified layout. The first portion is divided into a plurality of first sub-portions. The second portion is divided into a plurality of second sub-portions. Each second sub-portion is surrounded by two of the first sub-portions.Type: GrantFiled: May 26, 2021Date of Patent: February 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Wen Cho, Fu-Jye Liang, Chun-Kuang Chen, Chih-Tsung Shih, Li-Jui Chen, Po-Chung Cheng, Chin-Hsiang Lin
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Patent number: 11581300Abstract: A method is disclosed, including the following operations: arranging a first gate structure extending continuously above a first active region and a second active region of a substrate; arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure, in which the first gate via and the second gate via are arranged above the first active region and the second active region respectively; and arranging a first local interconnect between the first active region and the second active region, in which the first local interconnect is electrically coupled to a first contact disposed on the first active region and a second contact disposed on the second active region.Type: GrantFiled: November 6, 2020Date of Patent: February 14, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Charles Chew-Yuen Young, Chih-Liang Chen, Chih-Ming Lai, Jiann-Tyng Tzeng, Shun-Li Chen, Kam-Tou Sio, Shih-Wei Peng, Chun-Kuang Chen, Ru-Gun Liu
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Publication number: 20220362693Abstract: A filter is used for removing metallic contaminants in a solvent used in microcircuit fabrication. The filter includes a filter housing including a filter membrane for filtering solvent including metallic contaminants, and a magnet arranged about the filter housing and configured to generate a magnetic field to attract the metallic contaminants prior to the metallic contaminants entering the filter membrane. The magnet is arranged such that the magnetic field of the magnet is greater in a periphery of the filter housing compared to a central portion of the filter housing.Type: ApplicationFiled: July 26, 2022Publication date: November 17, 2022Inventors: Hsuan-Ying MAI, Hui-Chun LEE, Chun-Kuang CHEN, Tung-Hung FENG
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Publication number: 20220350242Abstract: The present disclosure provides a module for creating a metal-containing film, including a reactor chamber; an inlet for providing an organo-metallic precursor to the reactor chamber; and an inlet for providing a reactive gaseous species to react with the organo-metallic precursor to form a metal-containing film. The reactive gaseous species includes an element having three to five valence electrons and one or more radicals selected from hydrogen, C1-C3 alkyl, and C1-C3 alkoxyl. The present disclosure further relates to a method of creating the metal-containing film and a semiconductor structure associated therewith.Type: ApplicationFiled: April 22, 2022Publication date: November 3, 2022Inventors: Tse-An YEH, Montray LEAVY, Chun Kuang CHEN
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Publication number: 20220344170Abstract: A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench.Type: ApplicationFiled: July 11, 2022Publication date: October 27, 2022Inventors: Yung-Sung Yen, Chung-Ju Lee, Chun-Kuang Chen, Chia-Tien Wu, Ta-Ching Yu, Kuei-Shun Chen, Ru-Gun Liu, Shau-Lin Shue, Tsai-Sheng Gau, Yung-Hsu Wu
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Publication number: 20220223428Abstract: Exemplary methods of patterning a device layer are described, including operations of patterning a protector layer and forming a first opening in a first patterning layer to expose a first portion of the protector layer and a first portion of the hard mask layer, which are then are exposed to a first etch to form a first opening in the first portion of the hard mask layer. A second opening is formed in a second patterning layer to expose a second portion of the protector layer and a second portion of the hard mask layer. The second portion of the protector layer and the second portion of the hard mask layer are exposed to an etch to form a second opening in the second portion of the hard mask layer. Exposed portions of the device layer are then etched through the first opening and the second opening.Type: ApplicationFiled: March 28, 2022Publication date: July 14, 2022Inventors: Chi-Cheng Hung, Chun-Kuang Chen, De-Fang Chen, Wei-Liang Lin, Yu-Tien Shen
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Patent number: 11387113Abstract: A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench.Type: GrantFiled: October 26, 2020Date of Patent: July 12, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yung-Sung Yen, Chung-Ju Lee, Chun-Kuang Chen, Chia-Tien Wu, Ta-Ching Yu, Kuei-Shun Chen, Ru-Gun Liu, Shau-Lin Shue, Tsai-Sheng Gau, Yung-Hsu Wu
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Publication number: 20220163881Abstract: A phase-shift reticle for a photolithography process in semiconductor fabrication is provided. The reticle includes a substrate, a reflective structure, a pattern defining layer and a phase shifter. The reflective structure is disposed over the substrate. The pattern defining layer includes a first material and is deposited over the reflective structure. The pattern defining layer comprises a pattern trench. The phase shifter includes a second material and disposed in the pattern trench. A transmittance of the second material is different from a transmittance of the first material.Type: ApplicationFiled: November 18, 2021Publication date: May 26, 2022Inventors: Tse-An Yeh, Jun-Fei Zheng, Montray Leavy, Chun Kuang Chen