Abstract: An apparatus and method for fast phase aligned local generation of design clocks on a multiple FPGA system via clock generator replication is described. The apparatus includes a reference clock that generates a clock signal have a reference frequency and a plurality of programmable logic devices. Each programmable logic device includes phase locked loop circuitry that receives the clock signal from the reference clock and generates a local reference clock signal having a frequency based on the reference frequency and a clock generator that receives the local reference clock signal and generates local design clocks based on the local reference clock signal. Because each local design clock generator is synchronized by the same reference clock over a low skew line, the edges of the local design clocks are aligned.