Patents by Inventor Chun L. Liu

Chun L. Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12261240
    Abstract: A method removes defects in a dielectric layer, such as during fabrication of a device that emits light from hot electrons injected into an atomically two-dimensional material. An atomically two-dimensional material and the dielectric layer are adjoined. The dielectric layer is adapted to convey a variable electric field for modulating a wavelength of photons electronically emitted across a band structure of the atomically two-dimensional material. Laser pulses are strobed into the dielectric layer with sufficient cumulative energy to remove a majority of the defects in the dielectric layer without altering the atomically two-dimensional material.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: March 25, 2025
    Assignee: United States of America as represented by the Secretary of the Navy
    Inventors: Carlos Manuel Torres, Jr., Brad Chun-Ting Liu, Bienvenido Melvin L. Pascoguin
  • Patent number: 5566079
    Abstract: A method for producing a circuit layout comprising the steps of establishing high-level input parameters which identify input/output characteristics and high-level functional parameters of a data path, inputting the input parameters to a compiler, the compiler performing steps of creating a data path netlist by selecting data path components in response to the established high-level input parameters; and automatically selecting control logic for the data path components. The data path netlist is a high-level netlist of Boolean logic which can then easily be translated into a gate level implementation of the circuit layout.
    Type: Grant
    Filed: November 12, 1992
    Date of Patent: October 15, 1996
    Assignee: VLSI Technology, Inc.
    Inventors: Henry K. Jun, Chun L. Liu, Lin Yang, Kazuyoshi Moriya
  • Patent number: 5557532
    Abstract: A method for producing a circuit layout comprising the steps of establishing high-level input parameters which identify input/output characteristics and high-level functional parameters of a data path, inputting the input parameters to a compiler, the compiler performing steps of creating a data path netlist by selecting data path components in response to the established high-level input parameters; and automatically selecting control logic for the data path components. The data path netlist is a high-level netlist of Boolean logic which can then easily be translated into a gate level implementation of the circuit layout.
    Type: Grant
    Filed: November 12, 1992
    Date of Patent: September 17, 1996
    Assignee: VLSI Technology, Inc.
    Inventors: Henry K. Jun, Chun L. Liu, Lin Yang, Kazuyoshi Moriya