Abstract: In a fabrication method of a flash memory device, a first oxide layer is formed on the substrate in the memory cell region and in the peripheral circuit region. A first conductive layer is formed and defined to form a plurality of floating gates in the memory cell region. A second oxide layer and a silicon nitride layer are sequentially formed in the memory cell region and in the peripheral circuit region. The first conductive layer, the second oxide layer and the silicon nitride layer in the peripheral circuit region are removed. A doped region is formed in the peripheral circuit region. A third oxide layer is formed in the memory cell region and in the peripheral circuit region by wet rapid thermal oxidation. Thereafter, a second conductive layer is deposited to form concurrently a control gate in the memory cell region and a gate in the peripheral circuit region.

Abstract: In a fabrication method of a flash memory device, a first oxide layer is formed on the substrate in the memory cell region and in the peripheral circuit region. A first conductive layer is formed and defined to form a plurality of floating gates in the memory cell region. A second oxide layer and a silicon nitride layer are sequentially formed in the memory cell region and in the peripheral circuit region. The first conductive layer, the second oxide layer and the silicon nitride layer in the peripheral circuit region are removed. A doped region is formed in the peripheral circuit region. A third oxide layer is formed in the memory cell region and in the peripheral circuit region by wet rapid thermal oxidation. Thereafter, a second conductive layer is deposited to form concurrently a control gate in the memory cell region and a gate in the peripheral circuit region.

Abstract: The method for improving the performance of flash memory. A substrate is proved. A tunnel oxide layer is formed on the substrate. There two gate, structure are formed on the tunnel oxide layer. The gate structure including a first polysilicon layer as a floating gate, an interpoly dielectric layer such as ONO layer on the floating gate, a second polysilicon layer as a control gate on the interpoly dielectric layer. Moreover, the poly stringer is exit between the gates, wherein the poly stringer is unmovied after etched. Next, the oxygen free radical process cell oxidation is processed. The results ONO encroachment is very slightly then improvement of 6% GCR with pre-mixing gas process cell oxidation can increase operation speed by more than 5 times and eliminated poly stringer.

Abstract: A method for fabricating shallow trench isolation structures. A substrate is provided on which are sequentially stacked a buffer oxide layer and a mask layer. A plurality of trenches with different densities is formed in the stack of substrate/buffer oxide/mask layers. An insulating layer is formed over the substrate to fill the trenches. A planarized sacrificial layer is formed by spin coating polymer on the insulating layer. The sacrificial layer is completely removed by dry etching. A predetermined thickness of the insulating layer is removed such that a preliminary planarization of the insulating layer is obtained. By adjusting the etching parameters, the insulating layer is continuously removed by dry etching until the mask layer is exposed. The mask layer and buffer oxide layer are sequentially removed to expose a plurality of isolation structures with rounded surfaces.