Abstract: The present invention is related to a novel positive electrode active material for lithium-ion battery. The positive electrode active material is expressed by the following formula: Li1.2NixMn0.8-x-yZnyO2, wherein x and y satisfy 0<x?0.8 and 0<y?0.1. In addition, the present invention provides a method of manufacturing the positive electrode active material. The present invention further provides a lithium-ion battery which uses said positive electrode active material.

Abstract: The present disclosure provides a method for preparing a composition including mesenchymal stem cells, extracellular vesicles produced by the mesenchymal stem cells, and growth factors, the composition prepared by the method, and use of the composition for treating arthritis. The composition of the present disclosure achieves the effect of treating arthritis through various efficacy experiments.

Abstract: A system and a method for parameter optimization with adaptive search space and a user interface using the same are provided. The system includes a data acquisition unit, an adaptive adjustment unit and an optimization search unit. The data acquisition unit obtains a set of executed values of several operating parameters and a target parameter. The adaptive adjustment unit includes a parameter space transformer and a search range definer. The parameter space transformer performs a space transformation on a parameter space of the operating parameters according to the executed values. The search range definer defines a parameter search range in a transformed parameter space based on the sets of the executed values. The optimization search unit takes the parameter search range as a limiting condition and takes optimizing the target parameter as a target to search for a set of recommended values of the operating parameters.

Abstract: Disclosed herein is a complex, a contrast agent and the method for treating a disease related to CXCR4 receptor. The complex is configured to bind the CXCR4 receptor, and is used as a medicament for diagnosis and treatment of cancers and other indications related to the CXCR4 receptor.

Abstract: An acute kidney injury predicting system and a method thereof are proposed. A processor reads the data to be tested, the detection data, the machine learning algorithm and the risk probability comparison table from a main memory. The processor trains the detection data according to the machine learning algorithm to generate an acute kidney injury prediction model, and inputs the data to be tested into the acute kidney injury prediction model to generate an acute kidney injury characteristic risk probability and a data sequence table. The data sequence table lists the data to be tested in sequence according to a proportion of each of the data to be tested in the acute kidney injury characteristics. The processor selects one of the medical treatment data from the risk probability comparison table according to the acute kidney injury characteristic risk probability.

Abstract: A semiconductor structure is provided and includes a first gate structure, a second gate structure, and at least one local interconnect that extend continuously across a non-active region from a first active region to a second active region. The semiconductor structure further includes a first separation spacer disposed on the first gate structure and first vias on the first gate structure. The first vias are arranged on opposite sides of the first separation spacer are isolated from each other and apart from the first separation spacer by different distances.

Abstract: An enhancement mode high electron mobility transistor (HEMT) includes a group III-V semiconductor body, a group III-V barrier layer and a gate structure. The group III-V barrier layer is disposed on the group III-V semiconductor body, and the gate structure is a stacked structure disposed on the group III-V barrier layer. The gate structure includes a gate dielectric and a group III-V gate layer disposed on the gate dielectric, and the thickness of the gate dielectric is between 15 nm to 25 nm.

Abstract: Provided are semiconductor devices that include a first gate structure having a first end cap portion, a second gate structure having a second end cap portion coaxial with the first gate structure, a first dielectric region separating the first end cap portion and the second end cap portion, a first conductive element extending over the first gate structure, a second conductive element extending over the second gate structure, and a gate via electrically connecting the second gate structure and the second conductive element, with the first dielectric region having a first width and being positioned at least partially under the first conductive element and defines a spacing between the gate via and an end of the second end cap portion that exceeds a predetermined distance.

Abstract: The present disclosure is directed to methods and devices for devices including multiple die. A wafer is received having a plurality of die and a plurality of scribe lines. A dicing process is performed on the wafer. The dicing process includes identifying a first scribe line of the plurality of scribe lines, the first scribe line interposing a first die and a second die of the plurality of die; and performing a partial cut on the first scribe line. In embodiments, other scribe lines of the wafer are, during the dicing process, fully cut. After the dicing, the first die and the second die are mounted on a substrate such as an interposer. The first die and the second die are connected by a portion of the first scribe line, e.g., remaining from the partial cut, during the mounting.

Abstract: An integrated circuit package includes an interposer, the interposer including: a first redistribution layer, a second redistribution layer over the first redistribution layer in a central region of the interposer, a dielectric layer over the first redistribution layer in a periphery of the interposer, the dielectric layer surrounding the second redistribution layer in a top-down view, a third redistribution layer over the second redistribution layer and the dielectric layer, and a first direct via extending through the dielectric layer. A conductive feature of the third redistribution layer is coupled to a conductive feature of the first redistribution layer through the first direct via.

Abstract: A method includes depositing a first dielectric layer over a first conductive feature, depositing a first mask layer over the first dielectric layer, and depositing a second mask layer over the first mask layer. A first opening is patterned in the first mask layer and the second mask layer, the first opening having a first width. A second opening is patterned in a bottom surface of the first opening, the second opening extending into the first dielectric layer, the second opening having a second width. The second width is less than the first width. The first opening is extended into the first dielectric layer and the second opening is extended through the first dielectric layer to expose a top surface of the first conductive feature.

Abstract: A method is disclosed that includes performing a directional ion implantation process on a developed resist pattern to reduce roughness. A substrate can be tilted at a tilt angle with respect to the direction of an incoming ion beam. Ions can be directionally implanted at the tilt angle, along sidewall surfaces of the developed resist pattern to trim roughness from the sidewall surfaces. After implanting, the substrate can be rotated along the axis normal to a surface, and ions can then be directionally implanted at the tilt angle along the sidewall surfaces to further trim roughness from the sidewall surfaces of the developed resist pattern. The directional ion implantation process can be performed over a number of iterations, and during each iteration of the directional ion implantation process, the tilt angle can be adjusted so that the tilt angle is different than during previous iterations.

Abstract: A height adjustable semiconductor wafer support is provided. The height adjustable semiconductor wafer support includes a chuck for supporting a semiconductor wafer, an adjustment mechanism having a top surface for supporting the chuck, and a stage coupled to the adjustment mechanism such that movement of the top surface of the adjustment mechanism relative to the stage changes a distance between the top surface of the adjustment mechanism and a top surface of the stage.

Abstract: A height adjustable semiconductor wafer support is provided. The height adjustable semiconductor wafer support includes a chuck for supporting a semiconductor wafer, an adjustment mechanism having a top surface for supporting the chuck, and a stage coupled to the adjustment mechanism such that movement of the top surface of the adjustment mechanism relative to the stage changes a distance between the top surface of the adjustment mechanism and a top surface of the stage.

Abstract: A probe pin cleaning sheet with cleaning power and a manufacturing method thereof are disclosed, comprising a release layer, a cleaning layer, and a substrate. Thus, in the process that the probe pin pierces the cleaning layer, through the material of cleaning layer, and the cleaning grains of abrasive material contained in the cleaning material in the cleaning layer, the cleaning power is increased to scrape off dirt from the surface of probe pin. In addition, by the negative charges and lipophilic property of the silicone itself, the dirt on the probe pin can be transferred onto the cleaning layer.

Abstract: A probe cleaning sheet for preventing a probe pin damage and manufacturing method thereof, during the process of a probe pin puncturing the cleaning layer, the material of the cleaning layer and the plurality of high and low density cleaning particles of abrasive material contained in the high density cleaning material and the low density cleaning material are able to efficiently scrape away foreign material from the surface of the probe pin. In addition, the negative charge carried by the silicone itself and its lipophilic characteristics are used to transfer the foreign material on the probe pin to the cleaning layer, and the protective layer is used to prevent overpressure from the probe pin directly impacting the substrate and causing damage to the tips of the probe pin.

Abstract: The present application discloses a capacitive sensing device and a sensing method thereof. A plurality of driving signals corresponding to a plurality of driving codes are outputted to a plurality of driving electrodes, thereby, a plurality of sensing signal are generated on a plurality of sensing electrodes corresponding to the driving electrodes, where the sensing signals are decoded to sensing data by an operation circuit. Hereby, the calculation function of the operation circuit according to the present application may be simplified.

Abstract: The present disclosure relates to a method and an associated process tool. The method includes generating electromagnetic radiation that is directed toward a perimeter of a pair of bonded workpieces and toward a radiation sensor that is arranged behind the perimeter of the pair of bonded workpieces. The electromagnetic radiation is scanned along a vertical axis. An intensity of the electromagnetic radiation that impinges on the radiation sensor is measured throughout the scanning. Measuring the intensity includes recording a plurality of intensity values of the electromagnetic radiation at a plurality of different positions along the vertical axis extending past top and bottom surfaces of the pair of bonded workpieces. A position of an interface between the pair of bonded workpieces is determined based on a maximum measured intensity value of the plurality of intensity values.

Abstract: A pedal with anti-collision detection is installed on the rear of a vehicle. The pedal includes a pedal body and a radar device, with an insertion portion extending from the rear lateral side of the pedal body. Arc ribs are arranged from a rear lateral side of the pedal body toward a front lateral side of the pedal body at intervals, and straight ribs extend from the rear lateral side toward the front lateral side in a radial arrangement. The arc ribs and the straight ribs are interlaced, forming reinforcement spaces therebetween. An installation space is formed on an inner side of the front lateral side toward the rear lateral side for receiving the radar device. Each reinforcement space contains a reinforcement structure, thereby strengthening the structural strength of the pedal for protecting the radar device.

Abstract: In an embodiment, a method includes: placing a wafer on an implanter platen, the wafer including integrated circuit dies; measuring a position of the wafer by measuring a positions of an outer edge of the integrated circuit dies with a camera; determining an angular displacement between the position of the wafer and a reference position of the wafer; and rotating the implanter platen by the angular displacement.