Patents by Inventor Chun-Lin Lu

Chun-Lin Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220376079
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin spacer alongside a fin structure, a source/drain structure over the fin structure, and a salicide layer along a surface of the source/drain structure. A bottom portion of the salicide layer is in contact with the fin spacer. The semiconductor device structure also includes a capping layer over the salicide layer. A portion of the capping layer directly below the bottom portion of the salicide layer is in contact with the fin spacer. The semiconductor device structure also includes a dielectric layer over the capping layer. The dielectric layer is made of a different material than the capping layer.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 24, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiang-Ku SHEN, Jin-Mu YIN, Tsung-Chieh HSIAO, Chia-Lin CHUANG, Li-Zhen YU, Dian-Hau CHEN, Shih-Wei WANG, De-Wei YU, Chien-Hao CHEN, Bo-Cyuan LU, Jr-Hung LI, Chi-On CHUI, Min-Hsiu HUNG, Hung-Yi HUANG, Chun-Cheng CHOU, Ying-Liang CHUANG, Yen-Chun HUANG, Chih-Tang PENG, Cheng-Po CHAU, Yen-Ming CHEN
  • Patent number: 11503689
    Abstract: A circuit protection apparatus (100) is used to protect an LED drive circuit (200), and the circuit protection apparatus (100) includes a first switch unit (1) and a snubber circuit (3). The first switch unit (1) provides an electrical connection between an input terminal (100A) and the LED drive circuit (200) according to the normality of an input current (Iin) flowing through the input terminal (100A). The snubber circuit (3) provides a first delay time period (Td1) according to an input power (Vin). The snubber circuit (3) provides a start signal (Ss) to the LED drive circuit (200) according to the end of the first delay time period (Td1), and controls a first ground point (G1) of the snubber circuit (3) to be coupled to a second ground point (G2) of the LED drive circuit (200).
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: November 15, 2022
    Assignee: HERGY INTERNATIONAL CORP.
    Inventors: Cheng-Jen Lee, Yen-Lin Chen, Chun-Hung Lu
  • Publication number: 20220359977
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes: patch antennas, encapsulated by a first encapsulant; a device die, vertically spaced apart from the patch antennas, and electrically coupled to the patch antennas; and at least one redistribution structure, disposed between the patch antennas and the device die, and including electromagnetic bandgap (EBG) structures laterally surrounding each of the patch antennas.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 10, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Ping Wang, Chun-Lin Lu, Han-Ping Pu, Kai-Chiang Wu, Chung-Yi Hsu
  • Publication number: 20220336385
    Abstract: A package includes a semiconductor package including a semiconductor die and a first insulating encapsulation, a substrate, and a second insulating encapsulation. The first insulating encapsulation encapsulates the semiconductor die. The substrate includes a redistribution circuitry, wherein the substrate is electrically coupled to the semiconductor package through the redistribution circuitry. The second insulating encapsulation is disposed on and partially covers the substrate, wherein the substrate is sandwiched between the semiconductor package and the second insulating encapsulation.
    Type: Application
    Filed: June 29, 2022
    Publication date: October 20, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang Wang, Chung-Hao Tsai, Chen-Hua Yu, Chun-Lin Lu, Han-Ping Pu, Kai-Chiang Wu
  • Publication number: 20220322591
    Abstract: An information handling system printed circuit board includes solder pads that accept footprint compatible integrated circuits, such as charger integrated circuits that provide power with different choke circuit supporting components. Solder pads for supporting components include first and second conductive areas sized to accept a first supporting component, each of the first and second conductive areas including an intervening non-conductive area that manages positioning of a smaller second supporting component at solder reflow.
    Type: Application
    Filed: June 21, 2022
    Publication date: October 6, 2022
    Applicant: Dell Products L.P.
    Inventors: Yu-Lin Tsai, Chia-Hsien Lu, Chun-Min He, RungLung Lin, Chin-Chung Wu
  • Publication number: 20220320089
    Abstract: A semiconductor device is provided. The semiconductor device includes first channel nanostructures in a first device region, second channel nanostructures in a second device region, a dielectric fin at a boundary between the first device region and the second device region, a high-k dielectric layer surrounding each of the first channel nanostructures and each of the second channel nanostructures and over the dielectric fin, a first work function layer surrounding each of the first channel nanostructures and over the high-k dielectric layer and a second work function layer surrounding each of the second channel nanostructures and over the high-k dielectric layer and the first work function layer. The first work functional layer fully fills spaces between the first channel nanostructures and has an edge located above the dielectric fin. The second work functional layer fully fills spaces between the second channel nanostructures.
    Type: Application
    Filed: September 15, 2021
    Publication date: October 6, 2022
    Inventors: Lung-Kun CHU, Mao-Lin HUANG, Chung-Wei HSU, Jia-Ni YU, Chun-Fu LU, Kuo-Cheng CHIANG, Kuan-Lun CHENG, Chih-Hao WANG
  • Publication number: 20220310550
    Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first wafer including a first metal structure within a body of the first wafer. The semiconductor structure also includes a second wafer including a second metal structure within a body of the second wafer, where the first wafer is coupled to the second wafer at an interface. The semiconductor structure further includes a metal bonding structure coupled to the first metal structure and the second metal structure and extending through the interface.
    Type: Application
    Filed: October 6, 2021
    Publication date: September 29, 2022
    Inventors: Chun-Liang LU, Wei-Lin CHEN, Chun-Hao CHOU, Kuo-Cheng LEE
  • Publication number: 20220310564
    Abstract: A circuit structure for testing through silicon vias (TSVs) in a 3D IC, including a TSV area with multiple TSVs formed therein, and a switch circuit with multiple column lines and row lines forming an addressable test array, wherein two ends of each TSV are connected respectively with a column line and a row line. The switch circuit applies test voltage signals through one of the row lines to the TSVs in the same row and receives current signals flowing through the TSVs in the row from the columns lines, or the switch circuit applies test voltage signals through one of the column lines to the TSVs in the same column and receives current signals flowing through the TSVs in the column from the row lines.
    Type: Application
    Filed: July 13, 2021
    Publication date: September 29, 2022
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shou-Zen Chang, Chun-Lin Lu, Chun-Cheng Chen
  • Publication number: 20220302275
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first dielectric feature extending along a first direction, the first dielectric feature comprising a first dielectric layer having a first sidewall and a second sidewall opposing the first sidewall, a first semiconductor layer disposed adjacent the first sidewall, the first semiconductor layer extending along a second direction perpendicular to the first direction, a second dielectric feature extending along the first direction, the second dielectric feature disposed adjacent the first semiconductor layer, and a first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, and a portion of the first gate electrode layer is exposed to a first air gap.
    Type: Application
    Filed: March 19, 2021
    Publication date: September 22, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jia-Ni YU, Kuo-Cheng CHIANG, Mao-Lin HUANG, LUNG-KUN CHU, Chung-Wei HSU, Chun-Fu LU, CHIH-HAO WANG, KUAN-LUN CHENG
  • Publication number: 20220302299
    Abstract: The present application provides a semiconductor device and the method of making the same. The method includes recessing a fin extending from a substrate, forming a base epitaxial feature on the recessed fin, forming a bar-like epitaxial feature on the base epitaxial feature, and forming a conformal epitaxial feature on the bar-like epitaxial feature. The forming of the bar-like epitaxial feature includes in-situ doping the bar-like epitaxial feature with an n-type dopant at a first doping concentration. The forming of the conformal epitaxial feature includes in-situ doping the conformal epitaxial feature with a second doping concentration greater than the first doping concentration.
    Type: Application
    Filed: June 6, 2022
    Publication date: September 22, 2022
    Inventors: Chun-An Lin, Wei-Yuan Lu, Feng-Cheng Yang, Tzu-Ching Lin, Li-Li Su
  • Patent number: 11444173
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a fin structure over a substrate. The method also includes forming a gate structure over the fin structure. The method further includes forming fin spacers over sidewalls of the fin structure and gate spacers over sidewalls of the gate structure. In addition, the method includes forming a source/drain structure over the fin structure and depositing a dummy material layer to cover the source/drain structure. The dummy material layer is removed faster than the gate spacers during the removal of the dummy material layer. The method further includes forming a salicide layer over the source/drain structure and the fin spacers, and forming a contact over the salicide layer. The dummy material layer includes Ge, amorphous silicon or spin-on carbon.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: September 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsiang-Ku Shen, Jin-Mu Yin, Tsung-Chieh Hsiao, Chia-Lin Chuang, Li-Zhen Yu, Dian-Hau Chen, Shih-Wei Wang, De-Wei Yu, Chien-Hao Chen, Bo-Cyuan Lu, Jr-Hung Li, Chi-On Chui, Min-Hsiu Hung, Hung-Yi Huang, Chun-Cheng Chou, Ying-Liang Chuang, Yen-Chun Huang, Chih-Tang Peng, Cheng-Po Chau, Yen-Ming Chen
  • Patent number: 11432447
    Abstract: An information handling system printed circuit board includes solder pads that accept footprint compatible integrated circuits, such as charger integrated circuits that provide power with different choke circuit supporting components. Solder pads for supporting components include first and second conductive areas sized to accept a first supporting component, each of the first and second conductive areas including an intervening non-conductive area that manages positioning of a smaller second supporting component at solder reflow.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: August 30, 2022
    Assignee: Dell Products L.P.
    Inventors: Yu-Lin Tsai, Chia-Hsien Lu, Chun-Min He, RungLung Lin, Chin-Chung Wu
  • Publication number: 20220271148
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a substrate, and a gate structure formed over the fin structure. The gate structure includes a first layer, and a fill layer over the first layer. The gate structure includes a protection layer formed over the fill layer of the gate structure, and the protection layer is separated from the first layer by the fill layer.
    Type: Application
    Filed: April 9, 2021
    Publication date: August 25, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mao-Lin HUANG, Lung-Kun CHU, Chung-Wei HSU, Jia-Ni YU, Chun-Fu LU, Kuo-Cheng CHIANG, Kuan-Lun CHENG, Chih-Hao WANG
  • Patent number: 11424197
    Abstract: A package includes a semiconductor package including a semiconductor die and a first insulating encapsulation, a substrate, and a second insulating encapsulation. The first insulating encapsulation encapsulates the semiconductor die. The substrate includes a redistribution circuitry, wherein the substrate is electrically coupled to the semiconductor package through the redistribution circuitry. The second insulating encapsulation is disposed on and partially covers the substrate, wherein the substrate is sandwiched between the semiconductor package and the second insulating encapsulation.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: August 23, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang Wang, Chung-Hao Tsai, Chen-Hua Yu, Chun-Lin Lu, Han-Ping Pu, Kai-Chiang Wu
  • Publication number: 20220254722
    Abstract: A package structure includes an insulating encapsulation, at least one semiconductor die, a redistribution circuit structure, and first reinforcement structures. The at least one semiconductor die is encapsulated in the insulating encapsulation. The redistribution circuit structure is located on the insulating encapsulation and electrically connected to the at least one semiconductor die. The first reinforcement structures are embedded in the redistribution circuit structure. A shape of the package structure includes a polygonal shape on a vertical projection along a stacking direction of the insulating encapsulation and the redistribution circuit structure, and the first reinforcement structures are located on and extended along diagonal lines of the package structure.
    Type: Application
    Filed: April 25, 2022
    Publication date: August 11, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chun-Lin Lu, Han-Ping Pu, Kai-Chiang Wu
  • Patent number: 11398422
    Abstract: A package structure including a redistribution circuit structure, a wiring substrate, an insulating encapsulation, a buffer layer, a semiconductor device and a stiffener ring is provided. The redistribution circuit structure includes a first surface and a second surface opposite to the first surface. The wiring substrate is disposed on the first surface of the redistribution circuit structure. The insulating encapsulation is disposed on the first surface of the redistribution circuit structure and laterally encapsulating the wiring substrate. The buffer layer is disposed over the second surface of the redistribution circuit structure. The semiconductor device is disposed on the buffer layer, and the semiconductor device is electrically connected to the wiring substrate through the redistribution circuit structure. The stiffener ring is adhered with the buffer layer by an adhesive.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: July 26, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Lin Lu, Jiun-Yi Wu, Kai-Chiang Wu
  • Publication number: 20220230443
    Abstract: A method for detecting objects and labeling the objects with distances in an image includes steps of: obtaining a thermal image from a thermal camera, an RGB image from an RGB camera, and radar information from an mmWave radar; adjusting the thermal image based on the RGB image to generate an adjusted thermal image, and generating a fused image based on the RGB image and the adjusted thermal image; generating a second fused image based on the fused image and the radar information; detecting objects in the images, and generating, based on the fused image, another fused image including bounding boxes marking the objects; and determining motion parameters of the objects.
    Type: Application
    Filed: December 15, 2021
    Publication date: July 21, 2022
    Inventors: KAI-LUNG HUA, YUNG-YAO CHEN, SIN-YE JHONG, YO-CHENG CHEN, BA-LIN LIN, TZYY-YZONG LIN, CHENG-SHU WEN, YEN-PO WANG, CHUN-JUNG CHEN, TUNG-HSIN YANG, WEN-HSIANG LU, CHYI-JIA HUANG
  • Patent number: 11362009
    Abstract: Provided is a package structure and a method of fabricating the same. The package structure includes a die; a first encapsulant, laterally encapsulating the die; a first redistribution structure, disposed on the first encapsulant and the die; a second encapsulant, disposed on the first redistribution structure; an antenna pattern, embedded in the second encapsulant and electrically connected to the first redistribution structure; and a dielectric layer, covering the antenna pattern, wherein an upper surface of the second encapsulant is exposed by the dielectric layer, and a laser mark is formed within the upper surface of the second encapsulant.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: June 14, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Ta Lin, Chun-Lin Lu, Kai-Chiang Wu
  • Publication number: 20220181248
    Abstract: A package structure includes a first and a second conductive feature structures, a die, an insulator, an encapsulant, an adhesive layer, and a first through via. The die is located between the first conductive feature structure and the second conductive feature structure. The die is electrically connected to the second conductive feature structure. The insulator is disposed between the die and the first conductive feature structure. The insulator has a bottom surface in physical contact with a polymer layer of the first conductive feature structure. The encapsulant is located between the first conductive feature structure and the second conductive feature structure. The encapsulant is disposed on the insulator and laterally encapsulates the die and the insulator. The adhesive layer is disposed between the die and the insulator. The first through via extends through the encapsulant to connect to the first conductive feature structure and the second conductive feature structure.
    Type: Application
    Filed: February 22, 2022
    Publication date: June 9, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang Wang, Chun-Lin Lu, Kai-Chiang Wu
  • Patent number: 11342269
    Abstract: A package structure includes an insulating encapsulation, at least one semiconductor die, a redistribution circuit structure, and first reinforcement structures. The at least one semiconductor die is encapsulated in the insulating encapsulation. The redistribution circuit structure is located on the insulating encapsulation and electrically connected to the at least one semiconductor die. The first reinforcement structures are embedded in the redistribution circuit structure. A shape of the package structure includes a polygonal shape on a vertical projection along a stacking direction of the insulating encapsulation and the redistribution circuit structure, and the first reinforcement structures are located on and extended along diagonal lines of the package structure.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: May 24, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chun-Lin Lu, Han-Ping Pu, Kai-Chiang Wu