Patents by Inventor Chun-Lin Lu

Chun-Lin Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250140750
    Abstract: The present disclosure provides a memory device including a substrate including a first and a second surfaces opposite to each other, a first interconnection structure disposed on the first surface of the substrate, a first and second elements disposed in the substrate and/or the first interconnection structure, a second interconnection structure disposed on the first interconnection structure, and a third interconnection structure disposed on the second surface of the substrate. The first interconnection structure includes first wiring layers configured to be closest to the first and second elements. The third interconnection structure includes second wiring layers configured to be closest to the first and second elements. Each of the first and second elements includes a first electrical connection path through the first wiring layer and a second electrical connection path through the second wiring layer.
    Type: Application
    Filed: December 12, 2023
    Publication date: May 1, 2025
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Chun-Lin Lu, Chien-Ting Ho, Shou-Zen Chang
  • Publication number: 20250126809
    Abstract: A semiconductor structure including device structures arranged in a stack is provided. The device structures include substrates and through-substrate vias (TSVs). The TSVs are located in the substrates. The TSVs includes first TSVs. Each of the device structures includes the corresponding substrate and the corresponding first TSV. Each of the first TSVs passes through the corresponding substrate. The number of the TSVs in the endmost device structure is less than the number of the TSVs in another of the device structures. The first TSV in the endmost device structure and the first TSV in another of the device structures are aligned with each other and electrically connected to each other.
    Type: Application
    Filed: November 30, 2023
    Publication date: April 17, 2025
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Chun-Lin Lu, Chun-Cheng Chen, Ka Man So, Wei-Heng Chen, Shou-Zen Chang
  • Patent number: 12278149
    Abstract: A through-substrate via (TSV) test structure including a substrate, a first TSV, and a test device is provided. The substrate includes a test region. The first TSV is located in the substrate of the test region. The test device is located on the substrate of the test region. The test device and the first TSV are separated from each other. The shortest distance between the test device and the first TSV is less than 10 ?m.
    Type: Grant
    Filed: April 13, 2022
    Date of Patent: April 15, 2025
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Chun-Lin Lu
  • Publication number: 20250116941
    Abstract: A stitching method for an exposure process includes following steps. A wafer is provided. The wafer includes interposer regions, each of which includes a logic chip region, a first memory chip region, and a second memory chip region. The logic chip region is located between the first and second memory chip regions. A photoresist layer is formed on the wafer. First exposure processes are performed on the photoresist layer by applying a first photomask to form first shot regions in the photoresist layer. Second exposure processes are performed on the photoresist layer by applying a second photomask to form second shot regions in the photoresist layer. The first shot regions and the second shot regions are arranged alternately in a first direction. The first shot regions and the second shot regions are overlapped to form stitching regions, each of which is not located in the logic chip region.
    Type: Application
    Filed: November 14, 2023
    Publication date: April 10, 2025
    Applicants: Powerchip Semiconductor Manufacturing Corporation, AP Memory Technology Corporation
    Inventors: Shou-Zen Chang, Chun-Lin Lu, Cheng-Shu Ho, Kuo-Wei Liu, Kee-Wei Chung, Ru-Yi Cai
  • Publication number: 20250029949
    Abstract: A wafer stacking process is provided in the present invention, including steps of forming a silicon oxide layer on a sacrificial carrier, bonding the silicon oxide layer with a dielectric layer on a front side of a silicon substrate, performing a thinning process on the back side of the silicon substrate to expose TSVs therewithin, bonding the back side of the silicon substrate with another silicon substrate, repeating the thinning process and the process of bonding another silicon substrate above so as to form a wafer stacking structure, and performing a removing process to completely remove the sacrificial carrier.
    Type: Application
    Filed: November 1, 2023
    Publication date: January 23, 2025
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Chih-Feng Sung, Chih-Hao Chuang, Chun-Lin Lu, Shih-Ping Lee, Li-Han Chiu, Yi-Kai Wu
  • Publication number: 20240387979
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes: patch antennas, encapsulated by a first encapsulant; a device die, vertically spaced apart from the patch antennas, and electrically coupled to the patch antennas; and at least one redistribution structure, disposed between the patch antennas and the device die, and including electromagnetic bandgap (EBG) structures laterally surrounding each of the patch antennas.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Ping Wang, Chun-Lin Lu, Han-Ping Pu, Kai-Chiang Wu, Chung-Yi Hsu
  • Publication number: 20240379382
    Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor die and surrounding a sidewall of the semiconductor die with a dielectric material. The method further includes forming a post passivation interconnect (PPI) over the semiconductor die and electrically coupling the PPI with the semiconductor die. The method further includes molding the semiconductor die and the PPI into an integrated semiconductor package. The method further includes covering at least a portion of an outer surface of the integrated semiconductor package with a conductive layer, wherein the conductive layer is conformal to the morphology of the portion of the outer surface. Moreover, the method further includes forming a conductive path inside the integrated semiconductor package electrically coupled to the conductive layer and a ground terminal of the integrated semiconductor package.
    Type: Application
    Filed: May 29, 2024
    Publication date: November 14, 2024
    Inventors: SHOU ZEN CHANG, CHUN-LIN LU, KAI-CHIANG WU, CHING-FENG YANG, VINCENT CHEN, CHUEI-TANG WANG, YEN-PING WANG, HSIEN-WEI CHEN, WEI-TING LIN
  • Publication number: 20240363459
    Abstract: Provided is a package structure and an antenna structure. The package structure includes a die; a first encapsulant, laterally encapsulating the die; a first redistribution structure, disposed on the first encapsulant and the die; a second encapsulant, disposed on the first redistribution structure; an antenna pattern, embedded in the second encapsulant and electrically connected to the first redistribution structure; and a dielectric layer, covering the antenna pattern, wherein an upper surface of the second encapsulant is exposed by the dielectric layer, and a laser mark is formed within the upper surface of the second encapsulant.
    Type: Application
    Filed: July 4, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Ta Lin, Chun-Lin Lu, Kai-Chiang Wu
  • Patent number: 12132247
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes: patch antennas, encapsulated by a first encapsulant; a device die, vertically spaced apart from the patch antennas, and electrically coupled to the patch antennas; and at least one redistribution structure, disposed between the patch antennas and the device die, and including electromagnetic bandgap (EBG) structures laterally surrounding each of the patch antennas.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: October 29, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Ping Wang, Chun-Lin Lu, Han-Ping Pu, Kai-Chiang Wu, Chung-Yi Hsu
  • Publication number: 20240355684
    Abstract: A wafer stacking method includes the following steps. A first wafer is provided. A second wafer is bonded to the first wafer to form a first wafer stack structure. A first edge defect inspection is performed on the first wafer stack structure to find a first edge defect and measure a first distance in a radial direction between an edge of the first wafer stack structure and an end of the first edge defect away from the edge of the first wafer stack structure. A first trimming process with a range of a first width is performed from the edge of the first wafer stack structure to remove the first edge defect. Herein, the first width is greater than or equal to the first distance.
    Type: Application
    Filed: May 4, 2023
    Publication date: October 24, 2024
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Chih Feng Sung, Wei Han Huang, Ming-Jui Tsai, Yu Chi Chen, Yung-Hsiang Chang, Chun-Lin Lu, Shih-Ping Lee
  • Patent number: 12119303
    Abstract: A package structure includes an insulating encapsulation, at least one semiconductor die, a redistribution circuit structure, and first reinforcement structures. The at least one semiconductor die is encapsulated in the insulating encapsulation. The redistribution circuit structure is located on the insulating encapsulation and electrically connected to the at least one semiconductor die. The first reinforcement structures are embedded in the redistribution circuit structure. A shape of the package structure includes a polygonal shape on a vertical projection along a stacking direction of the insulating encapsulation and the redistribution circuit structure, and the first reinforcement structures are located on and extended along diagonal lines of the package structure.
    Type: Grant
    Filed: August 2, 2023
    Date of Patent: October 15, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chun-Lin Lu, Han-Ping Pu, Kai-Chiang Wu
  • Publication number: 20240332111
    Abstract: A semiconductor structure including a device wafer, a carrier structure, and a redistribution layer (RDL) structure is provided. The device wafer includes a first substrate, a first dielectric layer, first bonding pads, and a power via structure. The carrier structure includes the following components. A second substrate has a third surface and a fourth surface opposite to each other. A second dielectric layer is located on the third surface. Second bonding pads are located in the second dielectric layer. The second bonding pads are bonded to the first bonding pad, and the second dielectric layer is bonded to the first dielectric layer. A heat dissipation plate is located on the fourth surface. Through-substrates via (TSVs) pass through the second substrate. The TSV is electrically connected to the heat dissipation plate and the second bonding pad. The RDL structure is electrically connected to the power via structure.
    Type: Application
    Filed: April 20, 2023
    Publication date: October 3, 2024
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shou-Zen Chang, Chun-Lin Lu, Ming-Han Liao
  • Patent number: 12057358
    Abstract: Provided is a package structure and an antenna structure. The package structure includes a die; a first encapsulant, laterally encapsulating the die; a first redistribution structure, disposed on the first encapsulant and the die; a second encapsulant, disposed on the first redistribution structure; an antenna pattern, embedded in the second encapsulant and electrically connected to the first redistribution structure; and a dielectric layer, covering the antenna pattern, wherein an upper surface of the second encapsulant is exposed by the dielectric layer, and a laser mark is formed within the upper surface of the second encapsulant.
    Type: Grant
    Filed: May 15, 2022
    Date of Patent: August 6, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Ta Lin, Chun-Lin Lu, Kai-Chiang Wu
  • Patent number: 12046480
    Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor die and surrounding a sidewall of the semiconductor die with a dielectric material. The method further includes forming a post passivation interconnect (PPI) over the semiconductor die and electrically coupling the PPI with the semiconductor die. The method further includes molding the semiconductor die and the PPI into an integrated semiconductor package. The method further includes covering at least a portion of an outer surface of the integrated semiconductor package with a conductive layer, wherein the conductive layer is conformal to the morphology of the portion of the outer surface. Moreover, the method further includes forming a conductive path inside the integrated semiconductor package electrically coupled to the conductive layer and a ground terminal of the integrated semiconductor package.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: July 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shou Zen Chang, Chun-Lin Lu, Kai-Chiang Wu, Ching-Feng Yang, Vincent Chen, Chuei-Tang Wang, Yen-Ping Wang, Hsien-Wei Chen, Wei-Ting Lin
  • Publication number: 20240170386
    Abstract: A package structure includes a conductive feature structure, a die, an adhesive layer, an insulator, a through via, and an encapsulant. The die is disposed over the conductive feature structure. The adhesive layer is disposed below the die. The insulator is disposed between the adhesive layer and a polymer layer of the conductive feature structure. The through via extends through the insulator to connect to the conductive feature structure. The encapsulant is disposed on the insulator and the conductive feature structure, laterally encapsulating the die and the through via, and between the through via and the insulator. The insulator has a coefficient of thermal expansion less than a coefficient of thermal expansion of the encapsulant.
    Type: Application
    Filed: January 24, 2024
    Publication date: May 23, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang Wang, Chun-Lin Lu, Kai-Chiang Wu
  • Publication number: 20240162035
    Abstract: A multilayer stacking wafer bonding structure is provided in the present invention, including a logic wafer with a substrate and a logic circuit layer on the substrate, multiple memory wafers bonded sequentially on the logic circuit layer to form a first multilayer stacking structure, wherein each memory wafer includes a memory layer, a silicon layer on the memory layer and multiple oxide layers in trenches of the silicon layer, and the oxide layers in the memory wafers are aligned each other in a direction vertical to the substrate, and multiple through-oxide vias (TOV) extending through the memory layers and the oxide layers in the first multilayer stacking structure into the logic circuit layer, and the TOVs do not extend through any of the silicon layers.
    Type: Application
    Filed: January 16, 2023
    Publication date: May 16, 2024
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shou-Zen Chang, Chun-Lin Lu
  • Patent number: 11967558
    Abstract: A wafer stack structure includes an interlayer, a first wafer, and a second wafer. The interlayer has a first surface and a second surface opposite to the first surface. The intermediate layer includes a dielectric material layer and a redistribution layer embedded in the dielectric material layer. The first wafer is disposed on the first surface of the interlayer. The second wafer is disposed on the second surface of the interlayer. The second wafer is electrically connected to the first wafer through the redistribution layer of the interlayer.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: April 23, 2024
    Assignees: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shou-Zen Chang, Chun-Lin Lu, Jium-Ming Lin
  • Publication number: 20240088053
    Abstract: A semiconductor structure includes a first dielectric layer, a first die, a second die, a first molding, and a second molding. The first die is disposed under the first dielectric layer, and has a first surface facing the first dielectric layer and a second surface opposite to the first surface. The second die is disposed over the first dielectric layer, and has a third surface facing the first dielectric layer and a fourth surface opposite to the third surface. The first molding encapsulates the first die. The second molding is disposed over the first die and the first dielectric layer. The first surface of the first die and the third surface of the second die are in contact with the first dielectric layer. The fourth surface of the second die is partially exposed through the second molding and partially covered by the second molding.
    Type: Application
    Filed: November 23, 2023
    Publication date: March 14, 2024
    Inventors: CHEN-HUA YU, KAI-CHIANG WU, CHUN-LIN LU
  • Patent number: 11908787
    Abstract: A package structure includes a first and a second conductive feature structures, a die, an insulator, an encapsulant, an adhesive layer, and a first through via. The die is located between the first conductive feature structure and the second conductive feature structure. The die is electrically connected to the second conductive feature structure. The insulator is disposed between the die and the first conductive feature structure. The insulator has a bottom surface in physical contact with a polymer layer of the first conductive feature structure. The encapsulant is located between the first conductive feature structure and the second conductive feature structure. The encapsulant is disposed on the insulator and laterally encapsulates the die and the insulator. The adhesive layer is disposed between the die and the insulator. The first through via extends through the encapsulant to connect to the first conductive feature structure and the second conductive feature structure.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: February 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang Wang, Chun-Lin Lu, Kai-Chiang Wu
  • Patent number: 11894330
    Abstract: A method of manufacturing a semiconductor device includes providing a carrier, disposing a first pad on the carrier, forming a post on the first pad, and disposing a joint adjacent to the post and the first pad to form a first entire contact interface between the first pad and the joint and a second entire contact interface between the first pad and the post. The first entire contact interface and the second entire contact interface are flat surfaces.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: February 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun-Lin Lu, Kai-Chiang Wu, Ming-Kai Liu, Yen-Ping Wang, Shih-Wei Liang, Ching-Feng Yang, Chia-Chun Miao, Hao-Yi Tsai