Abstract: A package includes an interposer structure free of any active devices. The interposer structure includes an interconnect device; a dielectric film surrounding the interconnect device; and first metallization pattern bonded to the interconnect device. The package further includes a first device die bonded to an opposing side of the first metallization pattern as the interconnect device and a second device die bonded to a same side of the first metallization pattern as the first device die. The interconnect device electrically connects the first device die to the second device die.

Abstract: A bottom-emission light-emitting diode (LED) display includes a transparent substrate, a plurality of LEDs bonded on the substrate, a packaging layer formed on the substrate to cover the LEDs, and a reflecting layer formed on the packaging layer to reflect light emitted by the plurality of LEDs. The reflecting layer has a non-smooth shape or the packaging layer has different refractivities.

Abstract: A trimming method is provided. The trimming method includes the following steps. A first wafer including a substrate and a device layer over a first side of the substrate is provided. The first wafer is bonded to a second wafer with the first side of the substrate facing toward the second wafer. An edge trimming process is performed to remove a trimmed portion of the substrate from a second side opposite to the first side vertically downward toward the first side in a first direction along a perimeter of the substrate, wherein the edge trimming process results in the substrate having a flange pattern laterally protruding from the device layer and laterally surrounding an untrimmed portion of the substrate along a second direction perpendicular to the first direction.

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a UE. In certain configurations, the UE enters a first radio resource control (RRC) connection with a first base station of a first network. The UE receives, from the first base station, an indication that enables the UE to send a first request for deactivating or releasing resources used for communications with the first base station. In response to a determination to enter a second RRC connection with a second base station of a second network, the UE sends, to the first base station, the first request for deactivating or releasing the resources. The UE enters the second RRC connection with the second base station while maintaining the first RRC connection with the first base station.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin, a second fin and a third fin therebetween. A first insulating structure includes a first insulating layer formed between the first and third fins, a capping structure covering the first insulating layer, a first insulating liner covering sidewall surfaces of the first insulating layer and the capping structure and a bottom surface of the first insulating layer, and a second insulating liner formed between the first insulating liner and the first fin and between the first insulating liner and the third fin. The second insulating structure includes a second insulating layer formed between the second fin and the third fin and a third insulating liner formed between the second insulating layer and the second fin and between the second insulating layer and the third fin.

Abstract: A semiconductor structure includes a first dielectric layer, a first die, a second die, a first molding, and a second molding. The first die is disposed under the first dielectric layer, and has a first surface facing the first dielectric layer and a second surface opposite to the first surface. The second die is disposed over the first dielectric layer, and has a third surface facing the first dielectric layer and a fourth surface opposite to the third surface. The first molding encapsulates the first die. The second molding is disposed over the first die and the first dielectric layer. The first surface of the first die and the third surface of the second die are in contact with the first dielectric layer. The fourth surface of the second die is partially exposed through the second molding and partially covered by the second molding.

Abstract: The structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed. The method includes forming first and second nanostructured channel regions in first and second nanostructured layers, respectively, and forming first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively. The forming the first and second GAA structures includes selectively forming an Al-based n-type work function metal layer and a Si-based capping layer on the first nanostructured channel regions, depositing a bi-layer of Al-free p-type work function metal layers on the first and second nanostructured channel regions, depositing a fluorine blocking layer on the bi-layer of Al-free p-type work function layers, and depositing a gate metal fill layer on the fluorine blocking layer.

Abstract: A data transmission system is disclosed. The data transmission system includes at least one signal processing device, at least one conversion device, at least one antenna device, and at least one flexible printed circuit board. The at least one signal processing device is configured to generate or receive at least one data. The at least one conversion device is configured to transform between the at least one data and an optical signal. The at least one antenna device is configured to obtain the at least one data according to the optical signal, and configured to receive or transmit the at least one data wirelessly. The at least one flexible printed circuit board includes at least one conductive layer and at least one optical waveguide layer. The at least one optical waveguide layer is configured to transmit the optical signal.

Abstract: The present disclosure provides a multi-state one-time programmable (MSOTP) memory circuit including a memory cell and a programming voltage driving circuit. The memory cell includes a MOS storage transistor, a first MOS access transistor and a second MOS access transistor electrically connected to store two bits of data. When the memory cell is in a writing state, the programming voltage driving circuit outputs a writing control potential to the gate of the MOS storage transistor, and when the memory cell is in a reading state, the programming voltage driving circuit outputs a reading control potential to the gate of the MOS storage transistor.

Abstract: A micro device under test (DUT) carrier includes a carrier main body, a pusher and a spring. The carrier main body includes a plurality of bearing stages. Each bearing stage is utilized to bear a micro DUT. The pusher, operated to move from a locking position to an opening position, includes a pusher main body and a plurality of locking elements. Each locking element corresponds to each bearing stage, and is located next to each bearing stage. The spring is utilized to send the pusher back to the locking position, so that each locking element restricts movement of each micro DUT.

Abstract: A paper feeding mechanism includes a mechanical frame, a drive assembly mounted to the mechanical frame, an input tray, a pickup assembly driven by the drive assembly, an elevating assembly and a control assembly. The elevating assembly mounted to the mechanical frame and pivoted to a bottom of the rear end of input tray includes a drive shaft, a gear assembly and an elastic element. The rotating shaft defines two cam parts projecting beyond the rotating shaft. The rotating shaft is capable of rotating to make the cam parts press downward on or break away from the input tray so as to drive the input tray to swing downward or swing upward under an elastic push action of the elastic element. The control assembly includes a control system and a paper sensor controlled by the control system for detecting whether there is any paper on the input tray.

Abstract: A thin film transistor array substrate and repairing methods thereof are disclosed. The thin film transistor array substrate comprises openings in each pixel electrode, each capacitor electrode and each common line. The openings of the capacitor electrode and the common line are located in the opening of the pixel electrode. The opening of the capacitor electrode exposes a portion area of the capacitor electrode and the common line. The pixel electrode is coupled to the common line through a connecting conductive layer. The MII storage capacitor Cst is formed by the pixel electrode and the capacitor electrode. When the MII storage capacitor Cst fails, the MII storage capacitor Cst can be switched to the MIM storage capacitor Cst by laser repairing.

Abstract: A thin film transistor array substrate and repairing methods thereof are disclosed. The thin film transistor array substrate comprises openings in each pixel electrode, each capacitor electrode and each common line. The openings of the capacitor electrode and the common line are located in the opening of the pixel electrode. The opening of the capacitor electrode exposes a portion area of the capacitor electrode and the common line. The pixel electrode is coupled to the common line through a connecting conductive layer. The MII storage capacitor Cst is formed by the pixel electrode and the capacitor electrode. When the MII storage capacitor Cst fails, the MII storage capacitor Cst can be switched to the MIM storage capacitor Cst by laser repairing.

Abstract: A method of determining a composition of an integrated circuit feature, including collecting intensity data representative of spectral wavelengths of radiant energy generated by a plasma during plasma nitridation of an integrated circuit feature disposed on a substrate, analysing the in intensity data to determine a peak intensity at one of the wavelengths, and determining a component concentration of the feature based on the peak intensity.

Abstract: A method of determining a composition of an integrated circuit feature, including collecting intensity data representative of spectral wavelengths of radiant energy generated by a plasma during plasma nitridation of an integrated circuit feature disposed on a substrate, analyzing the intensity data to determine a peak intensity at one of the wavelengths, and determining a component concentration of the feature based on the peak intensity.

Abstract: The present disclosure provides a method for forming a gate stack structure for semiconductor devices. The disclosed method comprises steps such as forming a dielectric layer on a substrate; applying a plasma nitridation process on the formed dielectric layer; applying a first anneal process on the deposited dielectric layer; etching the dielectric layer to a predetermined thickness using a diluted etchant; applying a second anneal process using an oxygen environment on the etched dielectric layer after the etching; and forming a gate electrode layer on top of the dielectric layer. The etching makes the top portion of the etched dielectric layer have a significantly higher concentration of nitrogen than the lower portion of the etched dielectric layer so as the leakage current is significantly reduced.