Abstract: A plastic light-folding element includes an incident surface, an exit surface, at least one reflective surface, at least one connecting surface and at least one gate vestige structure. The incident surface is configured to lead an imaging light enter the plastic light-folding element. The exit surface is configured to lead the imaging light exit the plastic light-folding element. The reflective surface is configured to fold the imaging light. The connecting surface is connected to the incident surface, the exit surface and the reflective surface. The gate vestige structure is disposed on the connecting surface. At least one of the incident surface, the exit surface and the reflective surface includes an optical portion and an arc step structure, the arc step structure is disposed on a periphery of the optical portion, and an arc is formed by the arc step structure centered on the optical portion.

Abstract: Methods, systems, and computer program products are described for generating synthesizable netlists from register transfer level (RTL) designs to aid with semiconductor device design. These netlists provide RTL design information corresponding to a portion of a semiconductor device. A configuration tracer generates behavior information associated with the RTL design. A register compiler compiles a set of semiconductor devices based on one or more technologies and power, performance, and area (PPA) information related to the semiconductor device. Semiconductor devices generated by the register compiler that meet predefined power, performance, and area conditions are identified. Structural information for aligning the input/output ports of the semiconductor device is generated.

Abstract: A cash handling system and a cash transaction method are provided. The cash handling system includes at least one order terminal and a cash payment terminal. The cash payment terminal communicates with the order terminal. The order terminal captures a first image, and at least one piece of first face data is included in the first image. The order terminal obtains order data and generates client data according to the order data and the at least one piece of first face data. The at least one piece of first face data is linked to the order data. The cash payment terminal obtains the client data, and the client data includes the order data and the at least one piece of first face data. The cash payment terminal captures a second image. When specific face data appears in the second image, the cash payment terminal performs a payment operation according to specific order data linked to the specific face data.

Abstract: A plastic light-folding element includes an incident surface, an exit surface, at least one reflective surface, at least one connecting surface and at least one gate vestige structure. The incident surface is configured to lead an imaging light enter the plastic light-folding element. The exit surface is configured to lead the imaging light exit the plastic light-folding element. The reflective surface is configured to fold the imaging light. The connecting surface is connected to the incident surface, the exit surface and the reflective surface. The gate vestige structure is disposed on the connecting surface. At least one of the incident surface, the exit surface and the reflective surface includes an optical portion and an arc step structure, the arc step structure is disposed on a periphery of the optical portion, and an arc is formed by the arc step structure centered on the optical portion.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate stack structure formed over a substrate. The gate stack structure includes a gate electrode structure having a first portion and a second portion and a first conductive layer below the gate electrode structure. In addition, the first portion of the gate electrode structure is located over the second portion of the gate electrode structure, and a width of a top surface of the first portion of the gate electrode structure is greater than a width of a bottom surface of the second portion of the gate electrode structure.

Abstract: In an example embodiment, a user's session sequence data is utilized to provide a universal member representation that achieves one or more of the following goals: 1. Provides a user-level representation that enables the prediction of future actions based on historical interactions within different domains 2. Provides a user representation that allows better clarification of user intent (e.g., network builder, job seeker, profile scraper, etc.) 3. Members with similar/behaviors/intent are easily identified 4. Less sensitivity to activity levels of members.

Abstract: Methods, systems, and computer program products are described for generating synthesizable netlists from register transfer level (RTL) designs to aid with semiconductor device design. These netlists provide RTL design information corresponding to a portion of a semiconductor device. A configuration tracer generates behavior information associated with the RTL design. A register compiler compiles a set of semiconductor devices based on one or more technologies and power, performance, and area (PPA) information related to the semiconductor device. Semiconductor devices generated by the register compiler that meet predefined power, performance, and area conditions are identified. Structural information for aligning the input/output ports of the semiconductor device is generated.

Abstract: A method and system for migrating an existing ASIC design from one semiconductor fabrication process to another are disclosed herein. In some embodiments, a method for migrating the existing ASIC design comprises parsing the gate-level netlist one row at a time into one or more standard cells forming the ASIC design, forming a plurality of mapping tables having mapping rules for mapping the parsed one or more standard cells into equivalent target standard cells implemented in the second semiconductor fabrication process, mapping the parsed one or more standard cells into the equivalent target standard cells using the plurality of mapping tables, and generating a target gate-level netlist describing the ASIC design in terms of the equivalent target standard cells.

Abstract: In an example embodiment, a deep machine learning model ranks cohorts of users as well as cohorts of products in a single ranking. When utilized to determine which cohort members to display to a user, the system selects one user cohort and one product cohort as the “best” (e.g., the top ranked user cohort and the top ranked product cohort). This ranking may be based on a number of contextual and non-contextual features, including viewer features (characteristics of the user operating the user interface), viewee features (characteristics of or related to the litem that the user is viewing, such as the characteristics of another user whose profile the user is viewing), and viewer-viewee relationship features (indications about how the viewer and viewee are related, such as common schools, locations, places of employment, etc.).

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate stack structure formed over a substrate. The gate stack structure includes a gate electrode structure having a first portion and a second portion and a first conductive layer below the gate electrode structure. In addition, the first portion of the gate electrode structure is located over the second portion of the gate electrode structure, and a width of a top surface of the first portion of the gate electrode structure is greater than a width of a bottom surface of the second portion of the gate electrode structure.

Abstract: A digital-to-analog converter and an operation method thereof are provided. The digital-to-analog converter includes a current source module, a decoder, a change indicator, and a random number generator. The decoder is coupled to the current source module and receives a digital input signal. The change indicator is coupled to the decoder and provides an indication signal to the decoder. The random number generator is coupled to the change indicator and provides a random number signal to the change indicator. The change indicator generates an indication signal according to the random number signal, and the decoder generates a control signal to the current source module according to the digital input signal and the indication signal, so that the current source module generates an analog output signal corresponding to the digital input signal according to the control signal.

Abstract: An electronic device and a power system are provided. The electronic device includes a shelf casing and a filling component module. The shelf casing includes a plurality of side walls disposed around in sequence. The filling component module is disposed on the exterior of the shelf casing and adjacent to at least one of the plurality of side walls.

Abstract: A gate structure includes at least one spacer defining a gate region over a semiconductor substrate, a gate dielectric layer disposed on the gate region over the semiconductor substrate, a first work function metal layer disposed over the gate dielectric layer and lining a bottom surface of an inner sidewall of the spacer, and a filling metal partially wrapped by the first work function metal layer. The filling metal includes a first portion and a second portion, wherein the first portion is between the second portion and the semiconductor substrate, and the second portion is wider than the first portion.

Abstract: Provided herein are an oral care additive, an oral care composition, a method of preparing the same, an oral care kit and use thereof. The main ingredient of the oral care additive contains one or more of nicotinic acid, nicotinamide or derivatives thereof to supplement and increase the level of ?-nicotinamide adenine dinucleotide in the oral cavity, and various vitamin and coenzyme may be included as well to complement the function of the main ingredient. The additives and the application methods of the present invention retain the functionality of the existing oral care products while adding new efficacy, thereby providing a more comprehensive oral health management experience for the user.

Abstract: Systems and methods are described herein for attribute-point-based timing formal verification of application specific integrated circuit (ASIC) and system on chip (SoC) designs. A target circuit design having a first set of netlists and timing constraints is received. A plurality of key clock-pin-net-load-setting attributes are extracted from the first ported netlists and timing constraints. The clock-pin-net-load-setting attribute mismatch in the result report is checked between the target circuit design and a golden circuit design by comparing the plurality of target attributes with a plurality of golden attributes of the golden circuit design after the target design database is loaded for static timing analysis (STA).

Abstract: Systems, methods, and computer programs products are described for optimizing circuit synthesis for implementation on an integrated circuit. A register transfer level code description of logic behavior of a circuit. The register transfer level code description is converted into structurally defined circuit designs for multiple types of components and feature size technologies. A floor plan of each structurally defined circuit design is generated. A physically simulated circuit is created for each floor plan. A range of operating conditions is swept over to analyze power, performance, and area of each physically simulated circuit.

Abstract: A detection system and method for the migrating cell is provided. The system is configured to detect a migrating cell combined with an immunomagnetic bead. The system includes a platform, a microchannel, a magnetic field source, a coherent light source and an optical sensing module. The microchannel is configured to allow the migrating cell to flow in it along a flow direction. The magnetic field source is configured to provide magnetic force to the migrating cell combined with the immunomagnetic bead. The magnetic force includes at least one magnetic force component and the magnetic force component is opposite to the flow direction of the microchannel. The coherent light source is configured to provide the microchannel with the coherent light. The optical sensing module is configured to receive the interference light caused by the coherent light being reflected by the sample inside the microchannel.

Abstract: A digital-to-analog converter and an operation method thereof are provided. The digital-to-analog converter includes a current source module, a decoder, a change indicator, and a random number generator. The decoder is coupled to the current source module and receives a digital input signal. The change indicator is coupled to the decoder and provides an indication signal to the decoder. The random number generator is coupled to the change indicator and provides a random number signal to the change indicator. The change indicator generates an indication signal according to the random number signal, and the decoder generates a control signal to the current source module according to the digital input signal and the indication signal, so that the current source module generates an analog output signal corresponding to the digital input signal according to the control signal.

Abstract: Systems and methods are described herein for attribute-point-based timing formal verification of application specific integrated circuit (ASIC) and system on chip (SoC) designs. A target circuit design having a first set of netlists and timing constraints is received. A plurality of key clock-pin-net-load-setting attributes are extracted from the first ported netlists and timing constraints. The clock-pin-net-load-setting attribute mismatch in the result report is checked between the target circuit design and a golden circuit design by comparing the plurality of target attributes with a plurality of golden attributes of the golden circuit design after the target design database is loaded for static timing analysis (STA).

Abstract: Systems, methods, and computer programs products are described for optimizing circuit synthesis for implementation on an integrated circuit. A register transfer level code description of logic behavior of a circuit. The register transfer level code description is converted into structurally defined circuit designs for multiple types of components and feature size technologies. A floor plan of each structurally defined circuit design is generated. A physically simulated circuit is created for each floor plan. A range of operating conditions is swept over to analyze power, performance, and area of each physically simulated circuit.