Patents by Inventor Chun Ma

Chun Ma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250098280
    Abstract: A method includes forming a fin extending from a substrate; depositing a liner over a top surface and sidewalls of the fin, where the minimum thickness of the liner is dependent on selected according to a first germanium concentration of the fin; forming a shallow trench isolation (STI) region adjacent the fin; removing a first portion of the liner on sidewalls of the fin, the first portion of the liner being above a topmost surface of the STI region; and forming a gate stack on sidewalls and a top surface of the fin, where the gate stack is in physical contact with the liner.
    Type: Application
    Filed: December 2, 2024
    Publication date: March 20, 2025
    Inventors: Yi-Cheng Li, Pin-Ju Liang, Ta-Chun Ma, Pei-Ren Jeng, Yee-Chia Yeo
  • Publication number: 20250089286
    Abstract: A fin field effect transistor device structure includes a fin structure formed over a substrate. The structure also includes a liner layer and an isolation structure surrounding the fin structure. The structure also includes a gate dielectric layer formed over the fin structure and the isolation structure. The structure also includes a gate structure formed over the gate dielectric layer. The structure also includes source/drain epitaxial structures formed on opposite sides of the gate structure. The fin structure includes a protruding portion laterally extending over the liner layer.
    Type: Application
    Filed: November 22, 2024
    Publication date: March 13, 2025
    Inventors: Ta-Chun Ma, Yee-Chia Yeo
  • Publication number: 20250048716
    Abstract: Embodiments utilize a silicon germanium layer deposited to a low germanium percentage under a substrate. The substrate is used to form a field effect transistor FET structure. After formation of the FET, the silicon germanium layer is oxidized to drive germanium to a concentrated sublayer of the silicon germanium layer. The sublayer is used as a stop layer to remove the oxidized portion of the silicon germanium layer.
    Type: Application
    Filed: August 4, 2023
    Publication date: February 6, 2025
    Inventors: Yen Chuang, Ji-Yin Tsai, Jet-Rung Chang, Zheng Hui Lim, Ta-Chun Ma
  • Publication number: 20250048689
    Abstract: Methods of forming a stacked transistor are provided. One representative method may include patterning a first dummy nanostructure, a second dummy nanostructure, and a semiconductor nanostructure. The semiconductor nanostructure may be disposed between the first dummy nanostructure and the second dummy nanostructure. The first dummy nanostructure may comprise a first semiconductor material and the second dummy nanostructure may comprise a superlattice structure. The representative method may also include performing an etching process that simultaneously recesses the first dummy nanostructure to form a sidewall recess and removes the second dummy nanostructure to form an opening. The etching process selectively etches the superlattice structure at a faster rate than the first semiconductor material. The representative method may further include forming an inner spacer and an isolation structure in, respectively, the sidewall recess and the opening.
    Type: Application
    Filed: August 3, 2023
    Publication date: February 6, 2025
    Inventors: Ji-Yin Tsai, Zheng Hui Lim, Yen Chuang, Jet-Rung Chang, Ta-Chun Ma, Chii-Horng Li
  • Publication number: 20250022956
    Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, a nanostructured channel region disposed on the substrate, a gate structure surrounding the nanostructured channel region, a source/drain (S/D) region disposed adjacent to the nanostructured channel region, an etch stop layer (ESL) disposed on the S/D region, a stress liner disposed on the etch stop layer and configured to provide compressive stress in the nanostructured channel region, an inter-layer dielectric (ILD) layer disposed on the stress liner, and a contact structure disposed in the S/D region, ESL, stress liner, and ILD layer.
    Type: Application
    Filed: November 17, 2023
    Publication date: January 16, 2025
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Cheng LI, Jheng-Wei LIN, Ta-Chun MA
  • Patent number: 12191378
    Abstract: A fin field effect transistor device structure includes a fin structure formed over a substrate. The structure also includes a liner layer and an isolation structure surrounding the fin structure. The structure also includes a gate dielectric layer formed over the fin structure and the isolation structure. The structure also includes a gate structure formed over the gate dielectric layer. The structure also includes source/drain epitaxial structures formed on opposite sides of the gate structure. The fin structure includes a protruding portion laterally extending over the liner layer.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: January 7, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ta-Chun Ma, Yee-Chia Yeo
  • Patent number: 12191212
    Abstract: A method includes forming a fin extending from a substrate; depositing a liner over a top surface and sidewalls of the fin, where the minimum thickness of the liner is dependent on selected according to a first germanium concentration of the fin; forming a shallow trench isolation (STI) region adjacent the fin; removing a first portion of the liner on sidewalls of the fin, the first portion of the liner being above a topmost surface of the STI region; and forming a gate stack on sidewalls and a top surface of the fin, where the gate stack is in physical contact with the liner.
    Type: Grant
    Filed: May 5, 2022
    Date of Patent: January 7, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Cheng Li, Pin-Ju Liang, Ta-Chun Ma, Pei-Ren Jeng, Yee-Chia Yeo
  • Publication number: 20240428101
    Abstract: Embodiments are direct to methods and systems for authenticating a user and interpolating user preference embeddings. The systems generate, using a neural network trained to generate features based on training data comprising human voices spoken by a plurality of historical speakers inside a vehicle, input features based on a human voice of a current speaker inside the vehicle, and calculates similarities between an input vector of the input features and historical vectors in voiceprints of one or more enrolled users. After determining a similarity between the input vector and at least one historical vector in a voiceprint of an identified user is less than a threshold similarity, the systems authenticate the current speaker as the identified user, calculate a probabilistic notion based on the similarity, and apply the probabilistic notion to interpolate between downstream user preference embeddings associated with the identified user.
    Type: Application
    Filed: June 22, 2023
    Publication date: December 26, 2024
    Applicant: Toyota Connected North America, Inc.
    Inventors: Taylor Smith, King Chun Ma, Benjamin R. Resnick, Haris Siddiqui
  • Patent number: 12165380
    Abstract: An example method, apparatus, and computer-readable storage medium are provided to predict high-dynamic range (HDR) lighting from low-dynamic range (LDR) background images. In an example implementation, a method may include receiving low-dynamic range (LDR) background images of scenes, each LDR background image captured with appearance of one or more reference objects with different reflectance properties; and training a lighting estimation model based at least on the received LDR background images to predict high-dynamic range (HDR) lighting based at least on the trained model. In another example implementation, a method may include capturing a low-dynamic range (LDR) background image of a scene from an LDR video captured by a camera of the electronic computing device; predicting high-dynamic range (HDR) lighting for the image, the predicting, using a trained model, based at least on the LDR background image; and rendering a virtual object based at least on the predicted HDR lighting.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: December 10, 2024
    Assignee: GOOGLE LLC
    Inventors: Chloe LeGendre, Wan-Chun Ma, Graham Fyffe, John Flynn, Jessica Busch, Paul Debevec
  • Patent number: 12126469
    Abstract: A signal driver may include a plurality of distributed drivers along a differential transmission line. Each of the plurality of the distributed drivers may include: an output tap configured to receive a portion of an incoming signal of the signal driver; and a T-coil connected to an output node of the output tap. The differential transmission line is connected to and intercepted by a first terminal and a second terminal of the T-coil, and a plurality of T-coils of the plurality of the distributed drivers are distributed along and spaced apart on the differential transmission line.
    Type: Grant
    Filed: September 29, 2022
    Date of Patent: October 22, 2024
    Assignee: SEMTECH CORPORATION
    Inventors: Steven Greig Porter, Stanley Jeh-Chun Ma
  • Patent number: 12076771
    Abstract: A method for manufacturing a metal shell for casing of electronic product comprises stamping, squeezing and milling a sheet metal at a first area and a second area to form hinge side walls. The sheet metal on the periphery is stamped, squeezed, and milled to form side walls. Insert molding is performed at inner surface of the sheet metal to form an internal molded plastic part and a fine machining of the sheet metal is carried out. The metal shell is integrally formed from a single solid sheet, the manufacturing process is simple and economical as CNC processes are reduced.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: September 3, 2024
    Assignees: FUYU PRECISION COMPONENT(KUNSHAN)CO., LTD., Foxconn Technology Co., Ltd.
    Inventors: Ching-Sheng Sun, Fuh-Feng Tang, Ming-Hui Lin, Yong Yang, Ning Zhang, Hung-Chun Ma
  • Publication number: 20240248635
    Abstract: Techniques for storing metadata involve: storing first metadata associated with a system operation in a volatile memory of a storage system while the storage system is in a startup stage. The storage system does not perform read/write requests of a client during the startup stage. Such techniques further involve: suspending the system operation of the storage system during the startup stage in response to determining that the intermediate persistent storage device has failed. Such techniques further involve: storing the first metadata in the volatile memory into the persistent storage device. Such techniques further involve: storing the first metadata into the intermediate persistent storage device in response to determining that the intermediate persistent storage device is available again. Accordingly, the risk of losing metadata when the storage device is powered down can be reduced.
    Type: Application
    Filed: July 24, 2023
    Publication date: July 25, 2024
    Inventors: Yue Yang, Yousheng Liu, Chun Ma
  • Patent number: 12028055
    Abstract: A signal driver may include a variable termination resistor and a signal transmission line. The variable termination resistor may include one or more variable termination resistor units. Each of the one or more variable termination resistor units may include a switch connected to a first end node of the variable termination resistor; a T-coil connected to the switch; a first resistor connected to the first end node of the variable termination resistor and to the T-coil; and a second resistor connected to a second end node of the variable termination resistor and to the T-coil. The signal transmission line may be connected to the second end node of the variable termination resistor.
    Type: Grant
    Filed: October 10, 2022
    Date of Patent: July 2, 2024
    Assignee: SEMTECH CORPORATION
    Inventors: Steven Greig Porter, Stanley Jeh-Chun Ma
  • Publication number: 20240120912
    Abstract: A signal driver may include a variable termination resistor and a signal transmission line. The variable termination resistor may include one or more variable termination resistor units. Each of the one or more variable termination resistor units may include a switch connected to a first end node of the variable termination resistor; a T-coil connected to the switch; a first resistor connected to the first end node of the variable termination resistor and to the T-coil; and a second resistor connected to a second end node of the variable termination resistor and to the T-coil. The signal transmission line may be connected to the second end node of the variable termination resistor.
    Type: Application
    Filed: October 10, 2022
    Publication date: April 11, 2024
    Applicant: SEMTECH CORPORATION
    Inventors: Steven Greig PORTER, Stanley Jeh-Chun MA
  • Patent number: 11953991
    Abstract: Techniques for storage management involve determining a plurality of storage units to be reconstructed on a group of disks, the plurality of storage units being distributed on different disks in the group of disks. Such techniques further involve selecting, based on the distribution of the plurality of storage units on the group of disks, a group of storage units from the plurality of storage units so that different storage units in the group of storage units are distributed on different disks. Such techniques further involve performing concurrent reconstruction on the group of storage units.
    Type: Grant
    Filed: August 15, 2022
    Date of Patent: April 9, 2024
    Assignee: Dell Products L.P.
    Inventors: Chun Ma, Jianbin Kang, Hongpo Gao
  • Publication number: 20240113920
    Abstract: A signal driver may include a plurality of distributed drivers along a differential transmission line. Each of the plurality of the distributed drivers may include: an output tap configured to receive a portion of an incoming signal of the signal driver; and a T-coil connected to an output node of the output tap. The differential transmission line is connected to and intercepted by a first terminal and a second terminal of the T-coil, and a plurality of T-coils of the plurality of the distributed drivers are distributed along and spaced apart on the differential transmission line.
    Type: Application
    Filed: September 29, 2022
    Publication date: April 4, 2024
    Applicant: SEMTECH CORPORATION
    Inventors: Steven Greig PORTER, Stanley Jeh-Chun MA
  • Patent number: 11921551
    Abstract: A card riser for an information handling system includes a bottom surface, multiple connector slots in physical communication with the bottom surface, and a locking mechanism in physical communication with the bottom surface. Each connector slot is configured to receive a corresponding connector of a different one of multiple cards. When the locking mechanism is in an unlocked position, a different one of the cards is inserted within a different one of the connector slots. When the locking mechanism is in a locked position, the locking mechanism is placed in physical communication with each of the cards to securely hold the cards within the card riser.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: March 5, 2024
    Assignee: Dell Products L.P.
    Inventors: Hung Wen Wu, Liang-Chun Ma, Hsiang-Yin Hung
  • Patent number: 11854901
    Abstract: A device is manufactured by providing a semiconductor fin protruding from a major surface of a silicon substrate comprising silicon. A liner and a shallow trench isolation (STI) region are formed adjacent the semiconductor fin. A silicon cap is deposited over the semiconductor fin. The resulting cap consists of crystalline silicon in the portion over the semiconductor fin and consists of amorphous silicon in the portions over the liner and STI region. An HCl etch bake process is performed to remove the portions of amorphous silicon over the liner and the STI region.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Hsiung Yen, Ta-Chun Ma, Chien-Chang Su, Jung-Jen Chen, Pei-Ren Jeng, Chii-Horng Li, Kei-Wei Chen
  • Publication number: 20230352776
    Abstract: A housing structure includes a substrate, a first adhesive layer, and a silica gel layer. The substrate includes a first portion, and the first portion includes polybutylene terephthalate and glass fibers, the glass fibers and the polybutylene terephthalate are in a ratio between 40% and 50% by weight. The first adhesive layer is formed on the first portion. The first adhesive layer includes polysiloxane in a range of 2% to 5% by weight, acrylic resin in a range of 3% to 5% by weight, isopropanol in a range of 20% to 30% by weight, cyclohexane in a range of 20% to 30% by weight, and toluene in a range of 20% to 30% by weight. The silica gel layer is formed on the first adhesive layer, and the first adhesive layer bonds the silica gel layer to the first portion.
    Type: Application
    Filed: March 9, 2023
    Publication date: November 2, 2023
    Inventors: HUNG-CHUN MA, FUH-FENG TANG, CHING-SHENG SUN, HAI-PENG YAN
  • Publication number: 20230342071
    Abstract: A method, computer program product, and computing system for determining that one non-volatile random access memory (NVRAM) drive of a pair of NVRAM drives of a storage system is offline, thus defining an offline NVRAM drive and an online NVRAM drive. A virtual disk may be generated on a plurality of solid-state disks (SSDs) of the storage system. The contents of the online NVRAM drive may be copied to the virtual disk. The virtual disk may be exposed to the storage system as a representation of the offline NVRAM drive.
    Type: Application
    Filed: April 22, 2022
    Publication date: October 26, 2023
    Inventors: Xiaobo Zhang, Rongrong Shang, Chun Ma, Amitai Alkalay, Vamsi Vankamamidi